I followed the example in XMC_Peripheral_Library_v2.1.2/XMCLib/examples/XMC4500_series/I2C\I2C_TRANSFER
I think the code looks like this.
Assuming an XMC I2C master and XMC I2C slave (master send scenario).
My question when will load the master the new data? It is waiting the acknowledge and it has only 1 clock to load the data?
I think the code looks like this.
Assuming an XMC I2C master and XMC I2C slave (master send scenario).
My question when will load the master the new data? It is waiting the acknowledge and it has only 1 clock to load the data?
Code:
// MASTER
for (i=0; i<DATA_NUM+1; i++) {
while (USIC0_CH1->TCSR & USIC_CH_TCSR_TDV_Msk) ;
USIC0_CH1->PSCR |= USIC_CH_PSR_TBIF_Msk;
if (i == 0)
flags = XMC_I2C_CH_TDF_MASTER_START << 8U;
else if (i == DATA_NUM)
flags = XMC_I2C_CH_TDF_MASTER_STOP << 8U;
else
flags = XMC_I2C_CH_TDF_MASTER_SEND << 8U;
if (i < DATA_NUM)
USIC0_CH1->TBUF[0] = data[i] | flags; //START+ADDRESS+W or DATA
else
USIC0_CH1->TBUF[0] = flags; //STOP
if (i < DATA_NUM) {
while (!(USIC0_CH1->PSR & USIC_CH_PSR_IICMode_ACK_Msk)) ;
USIC0_CH1->PSCR |= USIC_CH_PSR_IICMode_ACK_Msk;
}
}