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How to know the state(ideal/Busy) of other cores(core1/2) from the master core(core0)

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Originally Posted by Venkat View Post
Hello,

I want to know the status of the other cores i.e, core 1 and core 2 CPU's are in ideal state or busy state from the core 0.

Is there any possible way to know the status of other cores.

Thank You.


Regards,

Venkat

Hi Venkat,

The status of the other cores can be obtained via the debug status register (DBGSR). The workings of this register is explained in the IFX Core Architecture User Manual.

Best regards,

Henk-Piet Glas
Technical Product Specialist

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