Hi,
Could anyone please help me to clarify which is the maximum frequency allowed in the MCLK/PCLK clock domain before entering deep sleep mode?
In the reference manual there is the following note, but I did not find any guidance, table or reference value.
XMC1400 AA-Step Microcontroller Series for Industrial Applications
Reference Manual V1.0 2015-10
Section: 14.3.2 System States
Subsection: Deep-Sleep State
Note: It is recommended to slow down the PCLK and MCLK before entering deep sleep mode to prevent a sudden load change that could cause a brownout reset.
My current setup:
XMC1404 running form main oscillator DCO1 = 48MHz = MCLK = PCLK
Could anyone please help me to clarify which is the maximum frequency allowed in the MCLK/PCLK clock domain before entering deep sleep mode?
In the reference manual there is the following note, but I did not find any guidance, table or reference value.
XMC1400 AA-Step Microcontroller Series for Industrial Applications
Reference Manual V1.0 2015-10
Section: 14.3.2 System States
Subsection: Deep-Sleep State
Quote:
Note: It is recommended to slow down the PCLK and MCLK before entering deep sleep mode to prevent a sudden load change that could cause a brownout reset.
XMC1404 running form main oscillator DCO1 = 48MHz = MCLK = PCLK