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Configuring PLL (writing N, P and K values into register) produces an interrupt?

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Hi all,

I have used the following code to configure a PLL module and, consequently, the rest of the clocks that are derived from fPLL signal. It is similar to the structure used in examples, in fact, I copied the structure to make sure there are no mistakes.

Code:

XMC_SCU_CLOCK_CONFIG_t clock_config =
{
                .syspll_config.n_div = 80U,
                .syspll_config.p_div = 2U,
                .syspll_config.k_div = 4U,
                .syspll_config.mode = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
                .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
                .enable_oschp = true,
                .enable_osculp = false,
                .calibration_mode = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
                .fstdby_clksrc = XMC_SCU_HIB_STDBYCLKSRC_OSI,
                .fsys_clksrc = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
                .fsys_clkdiv = 1U,
                .fcpu_clkdiv = 1U,
                .fccu_clkdiv = 1U,
                .fperipheral_clkdiv = 1U
};

However, the code "breaks" when the above configuration is called from inside the main() function. However, if I use the default settings, the code works. I have tracked the problem down to this particular command inside the XMC_SCU_CLOCK_StartSystemPll(source, mode, ndiv, pdiv, kdiv):

Code:

    SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~(SCU_PLL_PLLCON1_NDIV_Msk | SCU_PLL_PLLCON1_K2DIV_Msk |
                                  SCU_PLL_PLLCON1_PDIV_Msk)) | ((ndiv - 1UL) << SCU_PLL_PLLCON1_NDIV_Pos) |
                                  ((kdiv_temp - 1UL) << SCU_PLL_PLLCON1_K2DIV_Pos) |
                                  ((pdiv - 1UL)<< SCU_PLL_PLLCON1_PDIV_Pos));

The "Disassembly" window indicates that the code stops working properly at the following line, after stopping on '08000ccc' and stepping into '08000cce'.
Code:

1333          SCU_PLL->PLLCON1 = (uint32_t)((SCU_PLL->PLLCON1 & ~(SCU_PLL_PLLCON1_NDIV_Msk | SCU_PLL_PLLCON1_K2DIV_Msk |
08000cc8:  ldr r1, [pc, #252]      ; (0x8000dc8 <XMC_SCU_CLOCK_StartSystemPll+400>)
08000cca:  ldr r3, [pc, #252]      ; (0x8000dc8 <XMC_SCU_CLOCK_StartSystemPll+400>)
08000ccc:  ldr r2, [r3, #8]
08000cce:  ldr r3, [pc, #252]      ; (0x8000dcc <XMC_SCU_CLOCK_StartSystemPll+404>)

Regards,
Andrey

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