Hi Min Wei,
Thank you for your reply! Unfortunately, resetting TRAPDIS register nor doing so in conjunction with clearing trap requests with TRAPCLR did not solve the problem. I will continue to look into this issue and will make sure to post here if I happen to find a solution.
As a side note, perhaps this may be useful - I followed some steps listed in an article that describes how to "debug and diagnose Hard Faults on ARM Cortex-M CPUs". As a result of inserting a snippet that the website provides into the Default Hadnler, the "position" of the interrupt in the NVIC is copied into R2.The value that ended up in that register is '2', which is an NMI Handler? (Aside: I've heard that the name of the default interrupt that is shown in the "Disassmebler" is of no significance - but in case it is, it was listed as VADC3_G3_IRQHandler). Hopefully that sheds some more light on the issue.
Regards,
Andrey
Thank you for your reply! Unfortunately, resetting TRAPDIS register nor doing so in conjunction with clearing trap requests with TRAPCLR did not solve the problem. I will continue to look into this issue and will make sure to post here if I happen to find a solution.
As a side note, perhaps this may be useful - I followed some steps listed in an article that describes how to "debug and diagnose Hard Faults on ARM Cortex-M CPUs". As a result of inserting a snippet that the website provides into the Default Hadnler, the "position" of the interrupt in the NVIC is copied into R2.The value that ended up in that register is '2', which is an NMI Handler? (Aside: I've heard that the name of the default interrupt that is shown in the "Disassmebler" is of no significance - but in case it is, it was listed as VADC3_G3_IRQHandler). Hopefully that sheds some more light on the issue.
Regards,
Andrey