Solved MultiCAN+!
Turned out to be a little fidgety with the setup where MCR->CLKSEL needed to be set in two separate writes.
The Module Control Register MCR contains basic settings that determine the operation
of the MultiCAN+ module.
The write access to the lowest byte of the MCR register is possible only if the CCE bits
of all CAN nodes are set (NCRx.CCE bits). The NCRx.INIT bits will be automatically set
when the lowest byte of the MCR register is written, independent of the setting of the
CCE bits. The INIT bits have to be reset by software in order to activate the CAN nodes.
The reconfiguration of the clock source has to be done by using two writes: first a write
of zero to the CLKSEL bit field, and then a second write defining the new clock source.
Between the first and the second write a delay of 4 / fA + 2 / fCAN number of cycles must
be inserted by software, where fA is the frequency being switched off with the first write.
Exception: in case that fPERIPH is selected as the baud rate logic clock
(MCR.CLKSEL = 1), no delay cycles between the writes are necessary. In both cases,
simply using one write defining the new clock source is not allowed.
Note: If the baud rate logic is supplied from an unstable clock source, or no clock at all,
the CAN functionality is not guaranteed.
Turned out to be a little fidgety with the setup where MCR->CLKSEL needed to be set in two separate writes.
Quote:
The Module Control Register MCR contains basic settings that determine the operation
of the MultiCAN+ module.
The write access to the lowest byte of the MCR register is possible only if the CCE bits
of all CAN nodes are set (NCRx.CCE bits). The NCRx.INIT bits will be automatically set
when the lowest byte of the MCR register is written, independent of the setting of the
CCE bits. The INIT bits have to be reset by software in order to activate the CAN nodes.
The reconfiguration of the clock source has to be done by using two writes: first a write
of zero to the CLKSEL bit field, and then a second write defining the new clock source.
Between the first and the second write a delay of 4 / fA + 2 / fCAN number of cycles must
be inserted by software, where fA is the frequency being switched off with the first write.
Exception: in case that fPERIPH is selected as the baud rate logic clock
(MCR.CLKSEL = 1), no delay cycles between the writes are necessary. In both cases,
simply using one write defining the new clock source is not allowed.
Note: If the baud rate logic is supplied from an unstable clock source, or no clock at all,
the CAN functionality is not guaranteed.