Quote:
Originally Posted by cwunder
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Depending on how you are using the QSPI with DMA you could configure it for short data continuous mode while using the phase transition event (PT!) to control the data flow along with the BACON allowing for a hardware controlled CS..
It also depends on how you are writing to the TXFIFO whether you are using mixed entry or the Data/BACON addresses. With continuous mode the BACON.LAST bit controls when the frame ends. Depending on how you send the data you could use the GLOBALCON1.PT1 = DNA (Data Not Available) to know when to write the BACON.LAST=1 to close the frame after the last data write.
Since the SPI always receives data you can also key on the RX interrupt to know when the tx shift has completed.
It also depends on how you are writing to the TXFIFO whether you are using mixed entry or the Data/BACON addresses. With continuous mode the BACON.LAST bit controls when the frame ends. Depending on how you send the data you could use the GLOBALCON1.PT1 = DNA (Data Not Available) to know when to write the BACON.LAST=1 to close the frame after the last data write.
Since the SPI always receives data you can also key on the RX interrupt to know when the tx shift has completed.
I don't know whether the deassert CS until the received data is processed.
I think the RX interrupt idea is probably the best way to do this.
Thanks!
Toshi