Hi Lucas,
The Aurix does not have a dedicated I2S HW-module, but there is the possibilities to emulate I2S master and slave.
Master: For generating an I2S output, where the Aurix is the master the Queued SPI (QSPI) module can be used. To do so use the QSPI in simplex mode transmit mode. You will need two chip selects (SLSO), one for left/right and the second one as a dummy. The chip-select can be switched using the BACON entries.
Slave: In the slave mode the Aurix is responsible to receive the sound signals from an external master. To do so the Timer Input channels (TIM) of the Generic Timer Module (GTM) are used. E.g. TIM_0 is detecting the right or left noise while. TIM_1 is responsible to track the clock and trigger TIM_2 at a rising clock edge. TIM_2 will then track the data and store them through the ARU in the FIFO. By reaching the defined watermark in the FIFO the DMA is triggered to transfer the data to the memory.
Best regards,
Mr. AURIX™
The Aurix does not have a dedicated I2S HW-module, but there is the possibilities to emulate I2S master and slave.
Master: For generating an I2S output, where the Aurix is the master the Queued SPI (QSPI) module can be used. To do so use the QSPI in simplex mode transmit mode. You will need two chip selects (SLSO), one for left/right and the second one as a dummy. The chip-select can be switched using the BACON entries.
Slave: In the slave mode the Aurix is responsible to receive the sound signals from an external master. To do so the Timer Input channels (TIM) of the Generic Timer Module (GTM) are used. E.g. TIM_0 is detecting the right or left noise while. TIM_1 is responsible to track the clock and trigger TIM_2 at a rising clock edge. TIM_2 will then track the data and store them through the ARU in the FIFO. By reaching the defined watermark in the FIFO the DMA is triggered to transfer the data to the memory.
Best regards,
Mr. AURIX™