1. As per data sheet maximum instructions we can execute is 3, but as per the data sheet again, each core has 3 pipelines and they are Integer, load and loop and these will execute 3 instructions in parallel, does this mean that we can 9 pipelines and 9 instructions can be executes in parallel?
2. Boot up sequence of all the 3 cores. As per the datasheet, Core 0 is master which wakes up the other 2 cores, if this is correct then we have only one startup file but not 3.
3. Without using the keyword private0, shared etc. I would like to distribute the code and data to 3 cores, can you please inform how to do this. I tried example code but due to some technical problem that example code is not working on my PC. #pragmas are given in data sheet but I am unable to understand them, it would be great if you show us by taking an example.
4. Data sheet says that TC27x had RISC/DSP/MCU architecture, can I assume that 3 cores will have the dsp algorithms in build like FPU co-processor and all the 3 cores use RISC based register load/store architecture and performs MCU actions?
5. I heard that GPU is the common processor which is being used by other vendors to run the system at a faster rate and I cannot find GPU in our TC27x architecture in this would you please explain how do we make the things to run faster like processing images from camera, 3d images from radar/LIDAR, fusion images from camera/LIDAR/radar and data from many other sensors?
6. We assume that each core have its independent address as well as data registers, both 16 and 16 in number. Kindly clarify.
2. Boot up sequence of all the 3 cores. As per the datasheet, Core 0 is master which wakes up the other 2 cores, if this is correct then we have only one startup file but not 3.
3. Without using the keyword private0, shared etc. I would like to distribute the code and data to 3 cores, can you please inform how to do this. I tried example code but due to some technical problem that example code is not working on my PC. #pragmas are given in data sheet but I am unable to understand them, it would be great if you show us by taking an example.
4. Data sheet says that TC27x had RISC/DSP/MCU architecture, can I assume that 3 cores will have the dsp algorithms in build like FPU co-processor and all the 3 cores use RISC based register load/store architecture and performs MCU actions?
5. I heard that GPU is the common processor which is being used by other vendors to run the system at a faster rate and I cannot find GPU in our TC27x architecture in this would you please explain how do we make the things to run faster like processing images from camera, 3d images from radar/LIDAR, fusion images from camera/LIDAR/radar and data from many other sensors?
6. We assume that each core have its independent address as well as data registers, both 16 and 16 in number. Kindly clarify.