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DAVE4.3.2_DALI_interface

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How to work with the DALI interface in the release library Update_Site_Pack_2016-09-26?
Based on what I saw in the lessons on working with DALI, I should use the DALICG02.h library, but in the release there is only BCCU .h.

Attachment 2857
?????

Problem: Fatfs + watchdog

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The code
SDMMC->HOST_CTRL |= SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk | SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk;
doesn't works. The problem is still the same!
We have used another SD with different formatting and it is noticed that the one card does not show the problem longer than the other! Could there be a connection?

Regards,
Patrick

Sp37

TLE5012B E1000 with Arduino Mega

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I have recently purchased TLE5012B E1000 and trying to interface it with an Arduino Mega. I am receiving data but that seems like junk data. My SPI settings are SPI mode 0, SPI CLK 8 MHz. I am using the same circuit as in the datasheet for the SSC interface. I am using a delay of 10 microseconds before reading data from the sensor. The MOSI is configured as input before reading the data and then the data is read. Once the data is read MOSI pin is set back to output.
Below is the debug data I get on my serial monitor.
SPI: Sent 80, end of message
SPI: Sent 1, end of message
SPI: Received F0, end of message
SPI: Received 40, end of message
SPI: Received 5B, end of message
SPI: Received C9, end of message

This command is for enquiring the STAT register.

Code:

//read function in my library
void TLE5012::Read(char addr) {
  uint8_t dataOut;
  // variable to hold the command data
  TLE5012_Command cmd;

  // 1. Prepare command to be sent
  // read one single word without safety word
  cmd.Bits.len = 1;
  // read updated values
  cmd.Bits.upd = 0;
  // set starting address
  cmd.Bits.addr = addr;

  // this is a magic cookie to lock access to sys regs.
  if (addr > 4) {
    cmd.Bits.lock = TLE5012_MAGIC_SYSREG;
  } else {
    cmd.Bits.lock = 0;
  }

  // read operation
  cmd.Bits.rw = 1;

  // 2. start SPI, enable CS
  spiStart();

  // 3. send data on MOSI pin
  spiSend(cmd.w >> 8);
  spiSend(cmd.w);

  // 10 nops should cause about 250ns stall
        //delayMicroseconds(10);
        delay(2000);

       
  // 4. read adat from TLE5012
  dataOut = getByteFromSpi();
  dataOut = getByteFromSpi();
  dataOut = getByteFromSpi();
  dataOut = getByteFromSpi();

  // 5. Stop SPI, disable CS
  spiEnd();

  // return 0;
}

//main code
#include <spi_helper.h>
#include <TLE5012.h>

TLE5012 AngleSensor;
void setup() {
  // put your setup code here, to run once:
  Serial.begin(9600);
  AngleSensor.Init();
//  delay(100);
//  AngleSensor.Read(AVAL);
  delay(100);
  AngleSensor.Read(STAT);

}

void loop() {
  // put your main code here, to run repeatedly:

}

Can someone please help me out.

design.infineon.com

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The
problems
are
what?

What
are
the
problems?

Push Pull half bridge pwm using ccu8

The FIFO development in the CAN module of TC275

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Hello~thank you for spending time to read my thread !
Recently,I would like to develop the FIFO ability in the CAN module of TC275.(this one) But I I met some troubles.
If The FIFO is setted to 16,the using of sending data--16 circularly is normal.However,if there is one time that sending failed,or just sending successfully one time,the next adjustment don’t need sending data anymore. The library function I used is from infineon. Has anyone meet such a problems?
How to solve it?
Your help will be appreciated!
Have a nice day~ :)

C167CR-LM GPT1 Core Timer T3 How does it work?

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I don't understand all of your questions, so I will give you my feedback based on my understanding.

What Number would then stand in the Register T3 every tick?
It is the resolution at that in your case it is at 12.8us

How is the period or where is the period applied to?
In what purpose?

The period is the full 16-bits of the register so
w
here goes the Input frequency into?
This is the clock frequency is the rate in which T3 changes (increment or decrement)

What does the gated Mode or how does it work?
There is a section in the manual that describes this. In T3 Gated Timer Mode, the input clock of T3 is gated by the external input pin T3IN. You can control the level at which it gates the clock (think of it as run enable controlled by a port pin)


TC224 resets every 5 seconds

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Hello,

I am using the SW Framework (containing the demos, packages...). I have uploaded the MultiCAN example and I can see the messagess being sent at the correct cycle time in CANoe. The problem is that the core is reset every 5 seconds. I have read another thread containing info about the TC277 and I had made the changes specified there (remove R128 and place it in the blank space where R127 is supposed to be). Even with this change the core still is reset every 5 seconds. Does anyone know how can I make it work?

Will Dave support Tricore family in future, if yes, When?

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I have used Dave for XMC Family development for a while and get used to it.

Although it still have plenteous of weak points and bugs, its intuitive GUI, model based APP modules and flexibility are very helpful and convenient to use.

Recently, I start develop application with Tricore Family processor. Right now, I have only two choices for the full-functional tool-chain: Hightec and Tasking.
Unfortunately, both of them has a very steep learning curve. I am still struggling to master them.

Then my question is : Will Dave support Tricore Family developing in the future, if yes , when?

how to set reoccurring rtc alarm event for XMC1100

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hello
i can get rtc periodic event to execute properly (reoccurring every second or minute...)
and i can get rtc alarm event to execute properly (one time)
but what do i change/add to get an rtc alarm event to reoccur ?

is the external memory memory-mapped to the core, which is connected over EBU?

24GHz automotive radar development kit - Unreliable measurements

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Hi Forix,

I kept an object at a known distance from the radar, so that I know what distance output I should be getting. The attached Excel file has the results of my tests.
I repeated the tests multiple times, to see whether there was consistency.

I wrote scripts in Matlab to extract data from the sensor, according to the protocol mentioned in the manual of the radar kit. Infineon provides software for the microcontroller that runs the radar.

Attachment 2869

Thanks for your reply.
?????

How can compiler produce opcode that is illegal ?

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Infineon TC29x documentation says that executing illegal opcode causes a trap.

How can compiler produce code with illegal opcode? We're using Windriver Compiler / Assembler / Linker? Shouldn't illegal opcode cause a assembler or compiler error ?

Multiple SPI with different configuration

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To my knowledge, the DMA channels are only designed to transfer from one periphery to memory and vice vera.

Your problem is "simultaneously read", But the GPIO style common clock is slower than you need, right?

My suggestion: Try to run the code in SRAM. It will be much faster because the Flash has wait cycle.

Which XMC do you plan to use(XMC45?).

MPU for safety critical application

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Hi,

here is example to use MPU for protecting vector table against write access after it has been relocated to ram

extern int __vectortableram_start;

void SetupMpu(void)
{
#define MPU_RGN_NUMBER_VT 3 // region number and priority
#define MPU_RGN_SIZE_VT 8 // 512B =2^(8+1)
#define AP_VT 6 // access parameters r/r

#define MPU_RBAR_VALUE_VT ((uint32_t)__vectortableram_start)
#define MPU_RASR_VALUE_VT ((((uint32_t)MPU_RGN_SIZE_VT << PPB_MPU_RASR_SIZE_Pos) & PPB_MPU_RASR_SIZE_Msk) | \
((uint32_t)PPB_MPU_RASR_S_Msk) | \
((uint32_t)PPB_MPU_RASR_C_Msk) | \
(((uint32_t)AP_VT << PPB_MPU_RASR_AP_Pos) & PPB_MPU_RASR_AP_Msk) | \
((uint32_t)PPB_MPU_RASR_ENABLE_Msk))

// setup region address and region access parameters for VT
PPB->MPU_RNR = MPU_RGN_NUMBER_VT;
PPB->MPU_RBAR = MPU_RBAR_VALUE_VT;
PPB->MPU_RASR = MPU_RASR_VALUE_VT;

// enable MPU
PPB->MPU_CTRL = (uint32_t)(PPB_MPU_CTRL_ENABLE_Msk | PPB_MPU_CTRL_PRIVDEFENA_Msk);
__DSB();
__ISB();
}

write access will trigger exception memfault if installed.

rum

naming system of OptiMOS

hard switching

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Hard switching occurs when there is an overlap between voltage and current when switching the transistor on and off.
This overlap causes energy loss which can be minimized by increasing the di/dt and dv/dt.
However, fast changing di/dt or dv/dt causes EMI to be generated. Therefore the di/dt and dv/dt should be optimized to avoid EMI issues.

DMA - RTOS integrating

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Hello,

I'm working with Tricore AURIX TC234.
I'm trying to integrate an RTOS and everything is working until I add DMA transactions to the code application.

Source destination address for the transaction is where two GTM's registers are placed and destination address is where two variables are placed within a section protected by an MPU region.

I think that it shouldn't be an MPU-related problem because we're obtaining a Class 4 Trap, TIN 3 (Store Bus Error).
Trap-related registers contain the following information when it occurs:
DEADD = 0xF0011E02 (Where ECH field from TSR register is placed)
DATR.SBE = 1 (Store Bus Error)

The trap is happening just when we enable the transactions requests writing "1" in ECH.

Searching for this at the reference manual, I've read about the DMA Supervisor/User Mode, and its access protection registers related with their hardware resources' master tags identifiers.
The task within it is occurring is an unprivileged task (running in user mode), and I think that it could be related with.
I've tried to change the Hardare Resource 0 (Where used DMA channels are assigned) to User Mode (set in supervisor mode by default) but then, I'm having same Class 4 Trap, TIN 3 just when we try to write on MODE0.MODE bit.
Please notice that all fields within ACCEN0 are set to Enable.

How could it be related with my problem? Am I understanding something wrong?

Thanks.

XMC 4500 Ethernet failure

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Hi shenj,

Please try in the XMC_ETH_MAC_Init() function to add the following line at the end of the function:

Code:

...
  /* Disable MMC interrupt events */
  eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = 0x03ffffffU;
  eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = 0x03ffffffU;
  eth_mac->regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = 0x3fff3fffU;
...

The MMC IPC Receive interrupts were all enable and we did not clear them in the interrupt handler. Therefore after sometime with the occurrence of any of the MMC IPC Receive events the IRQ will fire continuously.

regards,
Jesus
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