Hi Ingo and Jesus,
Ingo, thank you for your response.
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Do you also use 16Bit demultiplexed Bus ?
No, we only use multiiplexed bus including A16 and A17 to have 18 address lanes.
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It is also very difficult to get a mini project for Jesus so that he can repoduce it because of the behaviour described above.
We managed to get a minimal project that shows the described behaviour.
Jesus, I attached the project to this post, named "zebu.zip".
The project shows a bus fault after about two seconds on our hardware.
If you could use one of our test-Hardware stations let me know, i think we could easily send you one.
We tried many different configurations on different Projects.
Let me sum up our findings during testing:
- We tested two configurations,
Config 1: Setting the input clock to the EBU to synchronous mode to the AHB. The config is provided in the attached file "Zebu/cfg/ebu_cfg47.h"
Config 2: Setting the input clock to the EBU to asynchronous mode to the AHB with Setting the EBUDIV divider in SCU_CLK.EBUDIV. This config is in the file zebu/cfg/ebu_cfg47_good.h.
Config 1: The EBU_CLK equals the clock of the AHB, we tried 144 MHz and 120 MHz. We tried many changes with the remining timing parameters. We verified these on the oscilloscope and read and write accesses worked without errors but we had Bus Fault Exceptions regardless of the exact Settings.
Config 2: The EBU_CLK is derived from the PLL with the divider SCU_CLK.EBUDIV. We set this divider with respect to fCPU either to 144 MHz: 8 or 120 MHz : 6.
We found few bus faults with fCPU = 144 MHz and until now not a single bus fault with fCPU = 120 MHz.
In our understanding, the reasons for the bus faults should not depend on external devices but on the internal AHB-Interface between the EBU and the Bus Matrix, so we tried changing the EBU-Clocking configuration and adapting the external Timings accordingly.
Jesus could you please review our configuration and give a statement to the described, different behaviours between the configurations? Is Config 2 a hundred percent safe with 120 MHz?
The thing is we need a 100% working configuration with no bus faults at all so that we can get to production with the XMC Controller.
We found a similar Problem regarding bus faults on Cortex m cpus, see
https://www.lpcware.com/content/foru...cd-display-tft
The solution there seems to be to clock the "EMC", which basically complys with the EBU, with less than the Maximum fCPU clock. This is even stated in the reference Manual of this LPC Controller.
Is there a similar hint for the XMC4700 EBU ?
Thank you for your help
Karl