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Connection closed by the GDB server - no source available for "0x0"

July 3, 2017, 9:24 am
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I have a similar problem, it terminates after downloadig the program.
Infineon left us alone.
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How to run Programm on XMC1100 without DAVE

July 4, 2017, 1:15 am
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Hi aurixuser,


Many thanks for your reply. I tried straightaway, then got diverted off. But back on the topic again now.


Yes, I've tried the Infineon XMC Flasher, with same results. I can see that the Flasher just launches J-Flash, with the 4 blue progress bars across the screen. Flasher says everything has programmed and verified OK. With Flasher, I've also tried an Erase before programming, and Verify command after, and all reports OK. I'm using the latest J-Flash, 6.16f, and Flasher even prompted to update the J-Flash firmware, which I OK'd. I'm also using the latest Java JRE runtime, jre-8u131-windows-x64. I updated to the latest, per the release notes for Flasher.

I've also tried J-Flash Lite, directly.

And of course, as launched by DAVE 4.3.2.


I've also tried the latest Infineon Memtool 4 (4.07.03 Build 4708 Frontend version 1.19.3 Server version 1.33.5), but got stuck at the dialogue titled 'Create or use default'. Apologies, I would attach, but I don't think I have enough Forum points yet, to be allowed to..

So, under XMC4300, I chose 'Use a default target configuration', then XMC4300, which is what we're using, then a choice of:

Starter Kits (Bootstrap Loader), and Infineon XMC4300 Relax Kit with XMC4300-F100x256 (BSL/ASC), and
Starter Kits (Bootstrap Loader), and Infineon XMC4300 Relax Kit with XMC4300-F100x256 (DAS)

I don't know what BSL/ASC or DAS are, so was stuck here. I will try and google.

Anyway, neither worked. They both reported a series of errors, saying 'Can't establish Connection to Target':

Message from component 'IMTMemtool' :
Can't connect to Target

Message from component 'CortexJtagIntf' :
Can't connect target !

Message from component 'CortexJtagIntf' :
Failed to connect target device !


The Change.. Target Interface Setup didn't give me any ungreyed options that matched the XMC Link SEGGER J-Link based probe we are using.


I also tried, the 'Create a new target configuration step by step' option. But that failed, just after it offered to add something named a 'UDE Add-In'.
It failed with these errors:

Message from component 'IMTMemtool' :
Component initialisation failed !

Message from component 'IMTMemtool' :
No core available for FLASH programming !


As mentioned, our project started life, as the Infineon example poject, for Modbus RTU.

In DAVE, I have Build Configurations > Set Active > Release, selected presently. As such, the project root, says 'Project [ Active - Release ]'. In Properties > Run/Debug Settings, I see a single entry, with the name 'Project Release'. If I click Edit.., to view its settings, I see on the Startup tab, it has 'Initial Reset and Halt'. Is that right, and intended? Is that the problem?

If I delete the 'Project Release' entry, and create a New one, or click the 'Restore Default' button, the same is true. So I imagine DAVE thinks the mentioned settings, are what is appropriate by default, for a release build.


Under Runtime Options, 'RAM application (reload after each reset/restart)', is unchecked. That pretty much describes, the behaviour we see. I wonder, is there perhaps a bug in DAVE, that has that checkbox, reversed ?


When I build our project, with Build Configurations > Set Active > Release selected, it comes out as 62896 bytes. With Build Configurations > Set Active > Debug selected, to comes out as 92032 bytes. Full optimisation (-O3), is selected presently for both.

So I'm fairly sure the release build, omits debug code.


In DAVE, with Build Configurations > Set Active > Release selected, if I click the DAVE toolbar Run button (green circled white triangle), the application downloads to our board, with the usual 4 blue progress bars, although they complete in a fraction of a second. Then, the following is reported:

SEGGER J-Link GDB Server V6.12j - Terminal output channel
Connection closed by the GDB Server.

Do you know, is that good? bad? normal?

The application seems to run, which I presume, means good. And I can close DAVE, and it carries on running, which is an improvement on what I was seeing originally.

However, if I powercycle our board, then our application software doesn't start. Completely dead, no startup LED transitions. So I don't think it it crashing. It is just, not starting.


Below, BTW, is what we see on-screen, when I click the DAVE Debug button (Beetle). Can you spot anything awry, in the following, maybe?

I am wondering, for example, whether an 0x0C000000 start, for our application, looks OK? Correct me if incorrect, but I heard that 0x0C000000 is non-cached FLASH, whereas 0x0800000 is cached FLASH. Perhaps one works, and the other doesn't, for application startup. But we would have inherited that, from the DAVE example project for Modbus RTU. And I don't know how one would go about changing, that.


SEGGER J-Link GDB Server V6.12j Command Line Version

JLinkARM.dll V6.12j (DLL compiled Feb 15 2017 18:01:10)

-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: on
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: XMC4300-F100x256
Target interface: SWD
Target interface speed: 1000kHz
Target endian: little

Connecting to J-Link...
J-Link is connected.
Firmware: J-Link Lite-XMC4200 Rev.1 compiled Apr 5 2017 11:59:07
Hardware: V1.00
S/N: 599000558
Checking target voltage...
Target voltage: 3.30 V
Listening on TCP/IP port 2331
Connecting to target...Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0x2000FF3C)
Read 2 bytes @ address 0x00000000 (Data = 0xFF3C)
Target interface speed set to 1000 kHz
Resetting target
Halting target CPU...
...Target halted (PC = 0x08000200)
R0 = E000ED08, R1 = 00000263, R2 = 02000080, R3 = C8000201
R4 = 00000536, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 00000000, R9 = 0C000004, R10= 00000000, R11= 00000000
R12= 00000000, R13= 1FFF0800, MSP= 1FFF0800, PSP= 00000000
R14(LR) = 000000ED, R15(PC) = 08000200
XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00
Reading all registers
Read 4 bytes @ address 0x08000200 (Data = 0xD074F8DF)
Read 2 bytes @ address 0x08000200 (Data = 0xF8DF)
Select auto target interface speed (1875 kHz)
Flash breakpoints enabled
Read 4 bytes @ address 0x08000200 (Data = 0xD074F8DF)
Downloading 668 bytes @ address 0x0C000000 - Verified OK
Downloading 4096 bytes @ address 0x0C020000 - Verified OK
Downloading 4096 bytes @ address 0x0C021000 - Verified OK
Downloading 4096 bytes @ address 0x0C022000 - Verified OK
Downloading 4096 bytes @ address 0x0C023000 - Verified OK
Downloading 4096 bytes @ address 0x0C024000 - Verified OK
Downloading 4096 bytes @ address 0x0C025000 - Verified OK
Downloading 4096 bytes @ address 0x0C026000 - Verified OK
Downloading 4096 bytes @ address 0x0C027000 - Verified OK
Downloading 4096 bytes @ address 0x0C028000 - Verified OK
Downloading 4096 bytes @ address 0x0C029000 - Verified OK
Downloading 4096 bytes @ address 0x0C02A000 - Verified OK
Downloading 4096 bytes @ address 0x0C02B000 - Verified OK
Downloading 4096 bytes @ address 0x0C02C000 - Verified OK
Downloading 4096 bytes @ address 0x0C02D000 - Verified OK
Downloading 4096 bytes @ address 0x0C02E000 - Verified OK
Downloading 4096 bytes @ address 0x0C02F000 - Verified OK
Downloading 4096 bytes @ address 0x0C030000 - Verified OK
Downloading 4096 bytes @ address 0x0C031000 - Verified OK
Downloading 4096 bytes @ address 0x0C032000 - Verified OK
Downloading 4096 bytes @ address 0x0C033000 - Verified OK
Downloading 4096 bytes @ address 0x0C034000 - Verified OK
Downloading 4096 bytes @ address 0x0C035000 - Verified OK
Downloading 1252 bytes @ address 0x0C036000 - Verified OK
Downloading 3696 bytes @ address 0x0C0364E4 - Verified OK
Read 4 bytes @ address 0x08000200 (Data = 0xD074F8DF)
Resetting target
Halting target CPU...
...Target halted (PC = 0x08000200)
Read 2 bytes @ address 0x08031CFC (Data = 0xE92D)
R0 = E000ED08, R1 = 00000263, R2 = 02000080, R3 = C8000201
R4 = 00000536, R5 = 00000000, R6 = 00000000, R7 = 00000000
R8 = 00000000, R9 = 0C000004, R10= 00000000, R11= 00000000
R12= 00000000, R13= 1FFF0800, MSP= 1FFF0800, PSP= 00000000
R14(LR) = 000000ED, R15(PC) = 08000200
XPSR 01000000, APSR 00000000, EPSR 01000000, IPSR 00000000
CFBP 00000000, CONTROL 00, FAULTMASK 00, BASEPRI 00, PRIMASK 00
Reading all registers
Read 4 bytes @ address 0x08000200 (Data = 0xD074F8DF)
Setting breakpoint @ address 0x08031CFC, Size = 2, BPHandle = 0x0001
Starting target CPU...
...Breakpoint reached @ address 0x08031CFC
Reading all registers
Read 4 bytes @ address 0x08031CFC (Data = 0x4FF0E92D)
Removing breakpoint @ address 0x08031CFC, Size = 2
Reading 64 bytes @ address 0x08031CC0
Reading 64 bytes @ address 0x08031D00
Reading 64 bytes @ address 0x08031D40
Reading 64 bytes @ address 0x08031D80
Read 2 bytes @ address 0x1FFF07D6 (Data = 0x0101)
Read 2 bytes @ address 0x1FFF07D6 (Data = 0x0101)


So, lots of things it could be. I can make a start on trying all the permutations. But it would be very much a blind investigation. It would be good to know how things are 'supposed' to be..

..I've worked with quite a few CPUs, from a few different vendors, and I must admit, I am struggling to understand why this most basic of operations, a Release build, doesn't just, well, work..!


Appreciating any insights aurixuser, or anyone, might be able to offer..


Best regards,

David
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Release build

July 4, 2017, 1:21 am
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Hi all,

I'm not sure on DAVE Forum etiquette, for referring to a post on another Infineon Forum. So do please let me know, if not appropriate. I know one shouldn't post the same thing, to two different Forums. Hence, I am just referring to another Forum. Specifically, to my posts to the 'Programm on XMC1100 without DAVE' topic, on the XMC Forum. I posted there, as our issue is related to that topic, started by 'smktec'. But perhaps, someone on the DAVE Forum, has some insights, on the issue. We're using an XMC4300. Link to that topic, is https://www.infineonforums.com/threa...0-without-DAVE

Best regards,

David
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UART via USB

July 4, 2017, 1:44 am
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Sorry Jesus,

I can't find it!
Do you have a link?

Regards,
Bernd
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24 GHz Radar

July 4, 2017, 4:35 am
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Hello all,

We have purchased 24 GHz Radar and were trying to do some measurements. However there are too many ghost targets appearing on the GUI. We are doing in open space indoor measurements.

Available Options:

Receiver : Rx1,
Gain : High

Target Threshold : 30

Gap Around Target : 1

Filter Static Objects : Off
RCS Compensation : Off


When these settings are done, we are not able to detect the correct range of the target or the angle of arrival.


We removed the metal plate from the current position (7 metres) and asked a human to walk with the same settings, unless he comes to 4.5 m -3.5 m , I dont see any target being detected at all , however we dont see many ghost targets appearing [ Case: Filter Static Objects :On]



I have gone through the code to get the relationship between Gap around the target and Target Threshold, however looks very tedious to find ? Can someone suggest what are the best settings to detect the target stable without ghost targets !!

Thanks and regards,
Kalyan
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How to create PLL loss of lock ?

July 4, 2017, 3:35 pm
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We're using Aurix Tricore SAKTC297 Microcontroller.

The microcontroller is wired with external Crystal / Ceramic Resonator Mode with external components.

Safety Management Unit (SMU) alarm will be triggered when PLL loses it lock on external clock.

How can I cause PLL to lose lock on external clock ? Is it possible to do if in software ?

Please see attached for brief PLL description.
?????
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Porting lwIP + ERIKA on TC29x board

July 5, 2017, 2:50 am
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Hello

I have issues while porting lwIP (lightweight IP) into ERIKA enterprise RTOS on TC297A-step board.
lwIP stack requires semaphore and mailbox implementations written into sys_arch.c file. For other operating systems like freeRTOS there are plenty of solutions avaliable on web, but has anyone made sys_arch.c file for ERIKA enterprise RTOS?
Do you have any hints on writing those architecture specific functions?

Best regards,
Josip
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SPI Slave WriteData Problem

July 5, 2017, 4:53 am
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Hi,
I have 2 XMC4500. 1 configured as Master, 1 as Slave.
I can receive the words, which are sent by the master in the slave.
But as soon i want to write data back via "SPI003_WriteData", the data, which the slave writes into the buffer will be transmitted completely different and the received bytes from the master will also be different.
And i dont understand why.
Can someone tell me, what i am doing wrong or what i am missing in the Slave implementation?

Using Dave 3.1.10

Used Configuration:
- Standard FullDuplex Mode
- Word length: 16
- Frame Length: 16
- Clock Phase Control: No Delay
- Clock Polarity Control: No Inversion
- Transmit/Receive LSB first
- Transmit and Receive FIFO: Size 2, Trigger Limit 1

Slave:
- Falling Edge trigger ( for triggering DX2T interrupt)
- Enable Slave Select Input Polarity

Master:
Code:

void cSpiMaster::WriteMessage(const uint16_t  *pSPISendData, const uint16_t& len)
{
 
  uint16_t tmp, i;

  uint8_t Status1 = 0;
  uint8_t Status2 = 0;
  /* Enable start of frame */
  EnableStartOfFrame(spi);

  /* Start sending len bytes of data from buffer */
  for (i=0; i<len-1; i++)
  {
          SPI001_ClearFlag(&spi,SPI001_RECV_IND_FLAG);
          SPI001_ClearFlag(&spi,SPI001_ALT_RECV_IND_FLAG);
          SPI001_WriteData(&spi, pSPISendData,SPI001_STANDARD);

          do
      {
                  Status1 = SPI001_GetFlagStatus(&spi,SPI001_RECV_IND_FLAG);
                  Status2 = SPI001_GetFlagStatus(&spi,SPI001_ALT_RECV_IND_FLAG);
      }while(!((Status1 == SPI001_SET) || (Status2 == SPI001_SET)));
          SPI001_ReadData(&spi,&tmp);        // dummy read
          pSPISendData++;
  }

  /* Enable end of frame */
  EnableEndOfFrame(spi);
  SPI001_ClearFlag(&spi,SPI001_RECV_IND_FLAG);
  SPI001_ClearFlag(&spi,SPI001_ALT_RECV_IND_FLAG);

  /* Send the last byte
    * After sending this data, frame will be finished since we
    * enable end of frame
    * */
    SPI001_WriteData(&spi, pSPISendData,SPI001_STANDARD);

    do
    {
            Status1 = SPI001_GetFlagStatus(&spi,SPI001_RECV_IND_FLAG);
            Status2 = SPI001_GetFlagStatus(&spi,SPI001_ALT_RECV_IND_FLAG);
    }while(!((Status1 == SPI001_SET) || (Status2 == SPI001_SET)));
    SPI001_ReadData(&spi, &tmp);  // dummy read

}

Slave: This Function will be called as often according my protocol length
Code:
bool cSpiSlave::ReadWord(uint16_t* word)
{
    *word = SPI_DUMMY_READ_WORD;
    uint16_t tmp = 0;
    uint8_t Status1 = 0;
    uint8_t Status2 = 0;

    do
    {
      Status1 = SPI003_GetFlagStatus(&spi,SPI003_RECV_IND_FLAG);
      Status2 = SPI003_GetFlagStatus(&spi,SPI003_ALT_RECV_IND_FLAG);
    }while(!((Status1 == SPI003_SET) || (Status2 == SPI003_SET)));

    /* Read data received from flash chip to buffer */
    SPI003_ReadData(&spi,&tmp);
    *word = tmp;
   
    // Clear flag
    SPI003_ClearFlag(&spi,SPI003_RECV_IND_FLAG);
    SPI003_ClearFlag(&spi,SPI003_ALT_RECV_IND_FLAG); 

    // Send read data back
    SPI003_WriteData(&spi,&tmp,SPI003_STANDARD);

    return true;
}
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xmc4500 wake up from hibernation bit HIBWK is never set

July 5, 2017, 5:14 am
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Hello,

I can send the system into hibernate and wake it up upon RTC event but the HIBWK of the RSTSTAT is never set.
I always have 7 in that register after start (or 15 when debugging). I also couldnt find anything related in the errata sheet.
Could someone shed some light on this?
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Connect both OPC-UA LWIP and TwinCAT SSC to XMC4800

July 5, 2017, 6:53 am
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Hi all,

I'm trying to connect XMC4800 with both OPCUA reference Client and also by TwinCAT SSC slave.

Is it possible ? I've merged the examples, ETHCAT_SSC_XMC48 with
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Connecting both OPC-UA LWIP and EtherCAT SSC slave to XMC48

July 5, 2017, 7:00 am
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Hi all,

I'm trying to connect both OPC-UA LWIP and EtherCAT SSC TwinCAT slave to XMC48

Is it possible ? I've merged examples ETHCAT_SSC_XMC48 and OPCUASERVER_LWIP_XMC47.

The SSC slave works fine, but OPC-UA Server throws BadRequestTimeout exception.

Please let me know I'm doing something wrong.
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What is the download link for EABI 3.0 Spec from Infineon for AURIX

July 5, 2017, 7:24 am
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Hello Support,
Can you please provide me the Version 3.0 EABI Spec from Infineon AURIX devices?
Thank you.
Regards
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USB VCOM APP integration

July 5, 2017, 9:38 am
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Hi jptalledo, I just started modifying the code and wondered if you got yours to work? Any issues?
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USBLIB_VIRTUALSERIAL_XMC45: Nothing is sent back to Host after reconnection

July 6, 2017, 12:52 am
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Hi,

We are checking the issue. In the mean time please use the DAVE CE example, USBD_VCOM_APP_EXAMPLE_XMC45.

Regards,
Jesus
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Problems with erasing and programming PFlash on AURIX TriCore (tc0), TC277-DC

July 6, 2017, 1:43 am
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Update:

By using the UDE Starterkit Debugger by PLS, I can now see that the Infineon FlashDemo code is entering trapcontext() when attempting to modify the PFlash sector.

Some time after successfully erasing the PFlash sector (again, not completely zeroed, but mostly), the code then jumps into the trap 3 handler:

0xA00F6060: 91 00 00 E8 MOVH.A a14,0x8000
0xA00F6064: D9 EE B6 61 LEA a14,[a14]0x19B6
0xA00F6068: DC 0E JI a14

Which subsequently calls _trapcontext():


0x800019B6: 0D 00 00 02 SVLCX
0x800019BA: 00 A0 DEBUG
0x800019BC: 8F 0F 43 41 OR d4,d15,0x30
0x800019C0: 6D FF E8 F3 CALL 0x80000190
0x800019C4: 0D 00 40 02 RSLCX
0x800019C8: 00 80 RFE
0x800019CA: 0D 00 00 02 SVLCX
0x800019CE: 00 A0 DEBUG
0x800019D0: 8F 0F 42 41 OR d4,d15,0x20
0x800019D4: 6D FF DE F3 CALL 0x80000190
0x800019D8: 0D 00 40 02 RSLCX
etc.

But upon executing the first instruction in _trapcontext() (SVLCX) the debugger loses step-control of the processor. If I break-in again, I end up back in the trap 3 handler. A look at the callstack shows these 2 addresses, like they're being called recursively:

0x800019B6
0x800019B6
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xA00F6080
0xC0000068
0x80000920
0x800007E8
0x8000062A
0x80001A6A
0x80001988

So I'm now reading TriCore Architecture Volume 1, section 6.3.4 Context Management (Trap Class 3). But if anyone has any tips, I'm all ears.

-Rob
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variable at fixed memory address

July 6, 2017, 2:33 am
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Hello Min Wei,

I have tested your suggestion and it works as far as I am in debug mode. If I switch to Release it doesn’t work any more. I found out the reason: Debug Setting -> Optimization Level: None, Release Setting -> Optimization Level: Optimize for size. If I change this in Release mode it works well again. But I have bigger code-size. I thought the KEEP instruction in the linker script would prevent this? Or am I doing something wrong?
Regards, Dirk
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Bldc motor commutation pattern

July 6, 2017, 1:01 pm
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Hello all,

Will the commutation output pattern be differed for various pole pairs?

For example;
when we use 1 pole pair: mech revolution(360°)/1 pole pair= 360°, that means rotor travelled one full rotation. To activate six MOSFET's the six step commutation pattern: 360°/6=60°,that means for every 60° every hall sensor changes its state.

when we use 5 pole pair: mech revolution(360°)/5 pole pairs=72°, that means rotor travelled only 72°. To activate six MOSFET's the six step commutation pattern: 72°/6=12°,that means for every 12° the hall sensors changes their state.

In both scenarios will the commutation output pattern be same or different?

Thanks
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XMC4200 DAC Problem

July 7, 2017, 4:56 am
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Hi Everyone,

I am working on XMC4200 DAC driver. In pattern generation mode, I want to generate a sine wave at the 8KHz frequency.
I am getting sine wave but the voltage is 2V only but as per reference manual max is 2.5V.
To increase voltage when I am selecting scale value - shift by 7 then I am, getting unknown waveform.

For sine wave 2V is max..?

My DAC Configurations

.en_mDACChannelSel = DAC_1,
.en_mModeSelect = DAC_PATTERN_GEN_MODE,
.en_mInputDataSel = DAC_UNSIGNED_INPUT_DATA,
.en_mOutputSignSel = DAC_SIGN_ENABLE,
.en_mPatternGenType = DAC_SINE,
.en_mScaleValue = DAC_SHIFT_LEFT_BY_6,
.en_mMulDiv = DAC_MULDIV_UPSCALE,
.en_mTriggerModeSelect = DAC_INTERNAL_TRIGGER,
.u32_mFrequencyDivider = 8000,
.en_mServiceReqEnable = DAC_SERVICE_REQ_DISABLE,

As input digital signal I am taking value between 0x000 - 0xFFF as sine wave.


Please help. I am waiting for your response.
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POSIF PDBG register always returns 0

July 7, 2017, 3:37 pm
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I have modified the BLDC_SCALAR_HALL_XMC44 app for the XMC4800 Relax Kit. I am using PORT 14, pins 7, 6, and 5 as POSIF0.IN0B, IN1B and IN2B respectively.
I am trying to use the PDBG register to monitor the HALL inputs.

The values of the GPIO pins match the HALL signals on the oscope. Here is a dump of the GPIO PORT 14:
Code:
*(int*)0x48028e24        int        0xf3df (Hex)
As you can see P14_7=1, P14_6=1, and P14_5=0.

When I dump the POSIF registers I expect to see these inputs reflected in the HSP field of the PDBG register.
However, that register is always 0. Here are all the POSIF registers including PCONF which shows that the PORT 14 pins are configured as the inputs to the POSIF.

Code:
*(POSIF_GLOBAL_TypeDef *)0x40028000        POSIF_GLOBAL_TypeDef        {...}       
        PCONF        volatile uint32_t        0x50451510 (Hex)       
        PSUS        volatile uint32_t        0       
        PRUNS        volatile uint32_t        0       
        PRUNC        volatile uint32_t        0       
        PRUN        const volatile uint32_t        1       
        RESERVED        const volatile uint32_t [3]        0x40028014       
        MIDR        const volatile uint32_t        11059200       
        RESERVED1        const volatile uint32_t [3]        0x40028024       
        HALP        const volatile uint32_t        0x32 (Hex)       
        HALPS        volatile uint32_t        0x26 (Hex)       
        RESERVED2        const volatile uint32_t [2]        0x40028038       
        MCM        const volatile uint32_t        513       
        MCSM        volatile uint32_t        8193       
        MCMS        volatile uint32_t        0       
        MCMC        volatile uint32_t        0       
        MCMF        const volatile uint32_t        0       
        RESERVED3        const volatile uint32_t [3]        0x40028054       
        QDC        volatile uint32_t        0       
        RESERVED4        const volatile uint32_t [3]        0x40028064       
        PFLG        const volatile uint32_t        4       
        PFLGE        volatile uint32_t        1048594       
        SPFLG        volatile uint32_t        0       
        RPFLG        volatile uint32_t        0       
        RESERVED5        const volatile uint32_t [32]        0x40028080       
        PDBG        const volatile uint32_t        0
Any help explaining whether the PDBG register can be relied on is appreciated.
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BSDL-files for XC2000

July 8, 2017, 9:21 am
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Good day!
Using the sak-xc2287m-104f80l device.
Does the xc2000m family support boundary scan or not?
As I inderstood, other xc2000 families like U or L support it.
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