Now it have RDM support
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Implementing RDM over DMX-512
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Get current system clock time
Hello ,
I am using infineon tricore tc299tf , i have initialised the STM module and now want to create an interrupt using STM compare registers but everytime i try to run it I am getting a TRAP 4 tin 3 error. Could you please help me with the same ?
I am using infineon tricore tc299tf , i have initialised the STM module and now want to create an interrupt using STM compare registers but everytime i try to run it I am getting a TRAP 4 tin 3 error. Could you please help me with the same ?
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Fail uploading hex file using SP37 programmer
I am using Keil IDE for programming sp370 pressure sensor IC. Once the project created, when uploading hex file using sp37 programmer, the following message occured.
ADDRESS OUT OF RANGE
FAILED to upload hex file
Can any one give suggestion?
ADDRESS OUT OF RANGE
FAILED to upload hex file
Can any one give suggestion?
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SPI slave MISO line issue (XMC4500 + XMC1201)
Hi Sebastian, hi Min Wei,
I have the same problem with a XMC1402. How did you solve this?
1) How can you enable/disable the slave MISO line?
2) PDL can only be set to 0 (the passive data level is 0) or 1(the passive data level is 1) but you can't set it to open drain...
Regards,
Juergen
I have the same problem with a XMC1402. How did you solve this?
1) How can you enable/disable the slave MISO line?
2) PDL can only be set to 0 (the passive data level is 0) or 1(the passive data level is 1) but you can't set it to open drain...
Regards,
Juergen
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PG-DSO-12-17 3D Model for IFX9201SG
Hi,
I'm looking for 3d Model in STP File for PG-DSO-12-17.
Many Thanks
Ying
I'm looking for 3d Model in STP File for PG-DSO-12-17.
Many Thanks
Ying
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SPI slave MISO line issue (XMC4500 + XMC1201)
Hi Sebastian, hi Min Wei,
I have the same problem with a XMC1402. How did you solve this?
1) How can you enable/disable the slave MISO line?
2) PDL can only be set to 0 (the passive data level is 0) or 1(the passive data level is 1) but you can't set it to open drain...
Regards,
Juergen
I have the same problem with a XMC1402. How did you solve this?
1) How can you enable/disable the slave MISO line?
2) PDL can only be set to 0 (the passive data level is 0) or 1(the passive data level is 1) but you can't set it to open drain...
Regards,
Juergen
↧
XMC ECAT0 Alias
I want to check or change the Station Alias.
However, it seems that the correct information can not be read or changed through the defined ECAT0.
Are there other conditions or procedures for use?
ECAT0 is defined in "XMC4300.h" as follows.
#define ECAT0 ((ECAT_Type *) ECAT0_BASE)
I read the information below but it is different from what I actually run on Ethercat.
ECAT_Type* pECAT_Reg = ECAT0;
nReadStation = pECAT_Reg->STATION_ADR;
nReadAlias = pECAT_Reg->STATION_ALIAS;
Of course, there is no change even if you input the following values at various timings.
pECAT_Reg->STATION_ALIAS = (uint16_t)nSetAlias;
However, it seems that the correct information can not be read or changed through the defined ECAT0.
Are there other conditions or procedures for use?
ECAT0 is defined in "XMC4300.h" as follows.
#define ECAT0 ((ECAT_Type *) ECAT0_BASE)
I read the information below but it is different from what I actually run on Ethercat.
ECAT_Type* pECAT_Reg = ECAT0;
nReadStation = pECAT_Reg->STATION_ADR;
nReadAlias = pECAT_Reg->STATION_ALIAS;
Of course, there is no change even if you input the following values at various timings.
pECAT_Reg->STATION_ALIAS = (uint16_t)nSetAlias;
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how to clear the buffer full in UART
hello,
I am also having this issue on same device and configuration. I am using both channels.
Can anyone give solution?
Thanks.
I am also having this issue on same device and configuration. I am using both channels.
Can anyone give solution?
Thanks.
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SP370 IC Selection on Keil IDE
I am developing a project using Infineon IC SP370. It has in-built 8051 microcontroller. I am using Keil IDE to develop the code for this chip.
When creating a new project, for chip selection, this SP370 IC is not available.
Will Keil IDE support this IC to develop the code?
When creating a new project, for chip selection, this SP370 IC is not available.
Will Keil IDE support this IC to develop the code?
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Aurix 2G Free Entry Tool Chain Interrupt on all cores
Hello,
I am working on tricore tc299tf and trying to initialize system timer interrupt. I have tried to use the examples that are explained here however my timer interrupt is still not working perfectly. I want to get tick every 1microsec. Could anyone help me with the issue ?
Thank you
Praktikant
I am working on tricore tc299tf and trying to initialize system timer interrupt. I have tried to use the examples that are explained here however my timer interrupt is still not working perfectly. I want to get tick every 1microsec. Could anyone help me with the issue ?
Thank you
Praktikant
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BTS6143 Max FET Voltage
The data sheet shows the BTS6143 max voltage to part of Vbb = 38 volts. During a turn off cycle of an inductive load ,the output clamped voltage is limited to Von(CL) -42 volts. Is the drive FET rated to Vbb+Von(CL) = 80 volts under these conditions?
I will be operating the device 30 volt max with an inductive clamped output at -25 volts (two diodes). Is this within the ratings?
Attachment 3510
I will be operating the device 30 volt max with an inductive clamped output at -25 volts (two diodes). Is this within the ratings?
Attachment 3510
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Flasher for TLE9879
Hi.
What program from infineon can I use to program tle9879?
J-Flash from Segger, and Evalkit TLE9879 are not friendly, and require a license.
Attachment 3511
What program from infineon can I use to program tle9879?
J-Flash from Segger, and Evalkit TLE9879 are not friendly, and require a license.
Attachment 3511
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Problems with FIFO/Gateway on XMCs 4400 Multican
By using gateway with FIFO (RxMO an gateway source side, TxFIFO MOs an gateway destination side) two pointers must be initialized
- pointer (defined via MOFCR register in the RxMO) for gateway feature
- pointer (defined via MOFCR register in the TxFIFO base object )
both pointers are working independently during CAN operation, i.e. the pointer of RxMO on the source side updates each time when CAN frame has been received, while the pointer of TxFIFO base object updates when CAN frame has been transmitted successfully on the destination CAN bus.
here is the ‘HW gateway feature’ has been initialized. that means ‘TxRQ is set’ in the gateway destination object automatically.
in case when the destination CAN node is disconnected or bus error/high load occurs the destination side, TxFIFO elements will be reloaded with new received CAN frames, but the pointer is not updated due to bus error. it may happen that you get an TxMO.MSGLST status but no FIFO overflow interrupt.
when you connect the CAN destination CAN node again, a new CAN frame may be sent out before old CAN frames on the destination bus, also a corrupted transmission sequence.
the max. configurable TxFIFO is limited due to total MSG objects (see please the data sheet or user’s manual) therefore it is to recommended to use ‘SW controlled gateway feature’ in order to avoid this problem.
here is an example code, please try it and contact us for further information and forward your feedback
- disable ‘automatical TxRQ set’ in the gateway source object
XMC_CAN_GATEWAY_InitSourceObject(&message33_rx_n1,
( (XMC_CAN_GATEWAY_CONFIG_t) {
2,
31,
2,
true, false (true=>HW controlled gateway; false=> SW controlled gateway)
true,
true,
true
}));
- enable RxOK interrupt for all TxFIFO message objects (base object und all slave objects: MO2..MO31) and assigned to the same interrupt line
- in the Interrupt service routine set TxRQ
void CAN_viSRN8(void) interrupt CAN_SRN8INT
{
ubBaseTxFIFOCUR= (ubyte) (CAN_HWOBJ[2].uwMOFGPRH & 0x00FF); // MO2 is the TxFIFO base, get CUR of TxFIFO
if (CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRL & 0x0010) // if the TxFIFO CUR pointered MO has MSGLST==1
CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRL = 0x0010; // reset MSGLST of this TxFIFO MO
else
CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRH = 0x0100; // set TxRQ in this TxFIFO MO
}
- pointer (defined via MOFCR register in the RxMO) for gateway feature
- pointer (defined via MOFCR register in the TxFIFO base object )
both pointers are working independently during CAN operation, i.e. the pointer of RxMO on the source side updates each time when CAN frame has been received, while the pointer of TxFIFO base object updates when CAN frame has been transmitted successfully on the destination CAN bus.
here is the ‘HW gateway feature’ has been initialized. that means ‘TxRQ is set’ in the gateway destination object automatically.
in case when the destination CAN node is disconnected or bus error/high load occurs the destination side, TxFIFO elements will be reloaded with new received CAN frames, but the pointer is not updated due to bus error. it may happen that you get an TxMO.MSGLST status but no FIFO overflow interrupt.
when you connect the CAN destination CAN node again, a new CAN frame may be sent out before old CAN frames on the destination bus, also a corrupted transmission sequence.
the max. configurable TxFIFO is limited due to total MSG objects (see please the data sheet or user’s manual) therefore it is to recommended to use ‘SW controlled gateway feature’ in order to avoid this problem.
here is an example code, please try it and contact us for further information and forward your feedback
- disable ‘automatical TxRQ set’ in the gateway source object
XMC_CAN_GATEWAY_InitSourceObject(&message33_rx_n1,
( (XMC_CAN_GATEWAY_CONFIG_t) {
2,
31,
2,
true, false (true=>HW controlled gateway; false=> SW controlled gateway)
true,
true,
true
}));
- enable RxOK interrupt for all TxFIFO message objects (base object und all slave objects: MO2..MO31) and assigned to the same interrupt line
- in the Interrupt service routine set TxRQ
void CAN_viSRN8(void) interrupt CAN_SRN8INT
{
ubBaseTxFIFOCUR= (ubyte) (CAN_HWOBJ[2].uwMOFGPRH & 0x00FF); // MO2 is the TxFIFO base, get CUR of TxFIFO
if (CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRL & 0x0010) // if the TxFIFO CUR pointered MO has MSGLST==1
CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRL = 0x0010; // reset MSGLST of this TxFIFO MO
else
CAN_HWOBJ[ubBaseTxFIFOCUR].uwMOCTRH = 0x0100; // set TxRQ in this TxFIFO MO
}
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XMC4500 multiCAN, getting MSGLST in a RXFIFO configuration
By using gateway with FIFO, normally one message object is configured as RxMO on gateway source side, and a couple of message objects are configured as TxFIFO MOs on gateway destination side.
the 4 RxFIFO mentioned here should be 4 TxFIFO on gateway destination side, right ?
regarding your problem “… experiencing MSGLST from a MO in the RXFIFO even though the FIFO is not full.” please see replies for in https://www.infineonforums.com/threa...4400-Multican?
each message object has 2 interrupt triggers (TxOk and RxOk interrupt). in case when a TxFIFO structure is used, the overflow interrupt (water level interrupt) of the TxFIFO base object is generated on RxOk interrupt of this base object, also 2 interrupt sources share on one interrupt trigger line.
extract from XMC user’s manual: If bit field MOFCRn.OVIE (“Overflow Interrupt Enable”) of the FIFO base object is set and the current pointer CUR becomes equal to MOFGPRn.SEL, a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt node RXINP of the base object after postprocessing of the received frame. Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set.
MSGLST indicates lost/or overwritten situation, but it can’t trigger interrupt.
the AppNote AP32300 has a detailed description about FIFO/Gateway with init. code, maybe it can help. https://www.infineon.com/dgdl/Infine...4ed91d6be32110
the 4 RxFIFO mentioned here should be 4 TxFIFO on gateway destination side, right ?
regarding your problem “… experiencing MSGLST from a MO in the RXFIFO even though the FIFO is not full.” please see replies for in https://www.infineonforums.com/threa...4400-Multican?
each message object has 2 interrupt triggers (TxOk and RxOk interrupt). in case when a TxFIFO structure is used, the overflow interrupt (water level interrupt) of the TxFIFO base object is generated on RxOk interrupt of this base object, also 2 interrupt sources share on one interrupt trigger line.
extract from XMC user’s manual: If bit field MOFCRn.OVIE (“Overflow Interrupt Enable”) of the FIFO base object is set and the current pointer CUR becomes equal to MOFGPRn.SEL, a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt node RXINP of the base object after postprocessing of the received frame. Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set.
MSGLST indicates lost/or overwritten situation, but it can’t trigger interrupt.
the AppNote AP32300 has a detailed description about FIFO/Gateway with init. code, maybe it can help. https://www.infineon.com/dgdl/Infine...4ed91d6be32110
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No confirmation email for Dave download
Hi,
I had the same problem when using Firefox 56.0.1 (64bit), solution was using Microsoft Browser.
I had the same problem when using Firefox 56.0.1 (64bit), solution was using Microsoft Browser.
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Switch from 1767 to 1782
Hi
I have a Tricore AUDO board which I upgraded from a TC1767 to TC1782 by replacing the processor and TLE7368-E I appear to be able to get my code running after commenting out the initial MAIN_vResetCheck() function created by DAvE it appears to lock up and prevent jtag from working when I write to the SCU_PLLCON0.
This board has been working fine when a TC1767 and is basically the EasyKit TC1782 board
Carl
I have a Tricore AUDO board which I upgraded from a TC1767 to TC1782 by replacing the processor and TLE7368-E I appear to be able to get my code running after commenting out the initial MAIN_vResetCheck() function created by DAvE it appears to lock up and prevent jtag from working when I write to the SCU_PLLCON0.
This board has been working fine when a TC1767 and is basically the EasyKit TC1782 board
Carl
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Product Information
Dear Community,
Please find here all information of the automotive products in NovalithIC family.
Visit us @:
Product overview:
https://www.infineon.com/cms/en/prod...ridge-driver/#
BTN8982:
https://www.infineon.com/cms/en/prod...ver/btn8982ta/
BTN8962:
https://www.infineon.com/cms/en/prod...ver/btn8962ta/
We highly recommend our customers to use the newest products mentioned above. Datasheets of old products of NovalithIC family are available upon request.
Best Regards,
Jing.N
Please find here all information of the automotive products in NovalithIC family.
Visit us @:
Product overview:
https://www.infineon.com/cms/en/prod...ridge-driver/#
BTN8982:
https://www.infineon.com/cms/en/prod...ver/btn8982ta/
BTN8962:
https://www.infineon.com/cms/en/prod...ver/btn8962ta/
We highly recommend our customers to use the newest products mentioned above. Datasheets of old products of NovalithIC family are available upon request.
Best Regards,
Jing.N
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Implementing RDM over DMX-512
Hi,
I'm also a newbie to the XMC series. What did you do to get RDM support working?
I'm also a newbie to the XMC series. What did you do to get RDM support working?
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SPI slave MISO line issue (XMC4500 + XMC1201)
Hi Juergen,
1. You enable/disable the MISO pin at the slave by configuring the pin as input/alternate ouput.
2. To configure the MISO as alternate output open drain instead of push pull
Are you using APPs? If so, in the Pin Settings tab you can change the mode from push pull to open drain easily.
Regards,
Jesus
1. You enable/disable the MISO pin at the slave by configuring the pin as input/alternate ouput.
Code:
// enable MISO
XMC_GPIO_SetMode(MISO, XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALTx);
// disable MISO
XMC_GPIO_SetMode(MISO, XMC_GPIO_MODE_INPUT_TRISTATE);
or
XMC_GPIO_SetMode(MISO, XMC_GPIO_MODE_INPUT_PULL_UP);Code:
XMC_GPIO_SetMode(MISO, XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALTx);Regards,
Jesus
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Errors in XMCLib
Hi,
Thanks for reporting the issue. It will be fixed in the next release.
Regards,
Jesus
Thanks for reporting the issue. It will be fixed in the next release.
Regards,
Jesus
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