September 4, 2018, 1:42 am
I also have same kind of problem while installing, at the last moment it was showing Missing DD file in the zip.
I think Update_Site_PACK_2016-05-17 version will solve that problem but unfortunately I am not getting that update.
Please share the link where I can find the mentioned update.
Thanks in advance
Regards
K Chandrasekhar
↧
September 4, 2018, 1:46 am
"the same project" means not only code but also settings/optimazitionItems... are all the same.
↧
↧
September 4, 2018, 7:13 am
Hello,
I tried to access the local data flash N25Q03 built into XMC4800 Relax board. Because there's no example for the 4800, I created a new SPI Master application with DAVE, then copied the required N25Q03 routines from the XMC4500 example to my project.
Works fine when running with low SPI clock speeds up to ~75 kHz. Everything above makes the dataflash chip return all zero bits on every attempt to read any data from it (e.g. device ID). Looked at the signals, but both MOSI, CLK and MISO signals look fine. Also, my example is using SPI in polled mode (no FIFO, no interrupts).
Is there something I should be aware of? Maybe performance of polled mode is too low to access the flash?
Attached you'll find the DAVE-generated SPI configuration.
Best regards,
Ernie
Code:
#include "spi_master.h"
static SPI_MASTER_STATUS_t SPI_MASTER_0_lInit(void);
/* Data Transmit pin from SPI_MASTER */
const SPI_MASTER_GPIO_t SPI_MASTER_0_MOSI =
{
.port = (XMC_GPIO_PORT_t *)PORT4_BASE,
.pin = (uint8_t)7
};
SPI_MASTER_GPIO_CONFIG_t SPI_MASTER_0_MOSI_Config =
{
.port_config =
{
.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1,
.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH,
.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE
},
.hw_control = XMC_GPIO_HWCTRL_DISABLED
};
/* Data Receive pin for SPI_MASTER */
const SPI_MASTER_GPIO_t SPI_MASTER_0_MISO =
{
.port = (XMC_GPIO_PORT_t *)PORT4_BASE,
.pin = (uint8_t)6
};
SPI_MASTER_GPIO_CONFIG_t SPI_MASTER_0_MISO_Config =
{
.port_config =
{
.mode = XMC_GPIO_MODE_INPUT_TRISTATE,
},
};
const SPI_MASTER_GPIO_t SPI_MASTER_0_SCLKOUT =
{
.port = (XMC_GPIO_PORT_t *)PORT4_BASE,
.pin = (uint8_t)2
};
const SPI_MASTER_GPIO_CONFIG_t SPI_MASTER_0_SCLKOUT_Config =
{
.port_config =
{
.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4,
.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH,
.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE
}
};
const SPI_MASTER_GPIO_t SPI_MASTER_0_SS_0 =
{
.port = (XMC_GPIO_PORT_t *)PORT4_BASE,
.pin = (uint8_t)3
};
const SPI_MASTER_GPIO_CONFIG_t SPI_MASTER_0_SS_0_Config =
{
.port_config =
{
.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1,
.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH,
.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE
},
.slave_select_ch = XMC_SPI_CH_SLAVE_SELECT_2
};
XMC_SPI_CH_CONFIG_t SPI_MASTER_0_Channel_Config =
{
.baudrate = 19200U,
.bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER,
.selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS,
.parity_mode = XMC_USIC_CH_PARITY_MODE_NONE
};
const SPI_MASTER_CONFIG_t SPI_MASTER_0_Config =
{
.channel_config = &SPI_MASTER_0_Channel_Config,
.fptr_spi_master_config = SPI_MASTER_0_lInit,
/* FIFO configuration */
.tx_fifo_size = (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_DISABLED,
.rx_fifo_size = (XMC_USIC_CH_FIFO_SIZE_t)XMC_USIC_CH_FIFO_DISABLED,
/* Clock Settings */
.shift_clk_passive_level = XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
.slave_select_lines = (uint8_t)1,
.leading_trailing_delay = (uint8_t)2,
.spi_master_config_mode = XMC_SPI_CH_MODE_STANDARD, /* spi master initial mode configured mode */
.transmit_mode = SPI_MASTER_TRANSFER_MODE_DIRECT,
.receive_mode = SPI_MASTER_TRANSFER_MODE_DIRECT,
.tx_cbhandler = NULL,
.rx_cbhandler = NULL,
.parity_cbhandler = NULL,
.mosi_0_pin = &SPI_MASTER_0_MOSI, /*!< mosi0 pin pointer*/
.mosi_0_pin_config = &SPI_MASTER_0_MOSI_Config,
.mosi_1_pin = &SPI_MASTER_0_MISO,
.mosi_1_pin_config = &SPI_MASTER_0_MISO_Config,
.mosi_2_pin = NULL,
.mosi_2_pin_config = NULL,
.mosi_3_pin = NULL,
.mosi_3_pin_config = NULL,
.sclk_out_pin_config = &SPI_MASTER_0_SCLKOUT_Config,
.sclk_out_pin = &SPI_MASTER_0_SCLKOUT,
.slave_select_pin = {&SPI_MASTER_0_SS_0, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL
},
.slave_select_pin_config = {&SPI_MASTER_0_SS_0_Config, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL
},
.tx_sr = (SPI_MASTER_SR_ID_t)SPI_MASTER_SR_ID_0,
.rx_sr = (SPI_MASTER_SR_ID_t)SPI_MASTER_SR_ID_0,
};
SPI_MASTER_RUNTIME_t SPI_MASTER_0_runtime =
{
.spi_master_mode = XMC_SPI_CH_MODE_STANDARD, /* spi master transmission mode */
.word_length = 8U,
.dx0_input = SPI_MASTER_INPUT_E,
.dx0_input_half_duplex = SPI_MASTER_INPUT_INVALID,
.tx_data_dummy = false,
.rx_data_dummy = true,
.tx_busy = false,
.rx_busy = false
};
SPI_MASTER_t SPI_MASTER_0 =
{
.channel = XMC_SPI2_CH1, /* USIC channel */
.config = &SPI_MASTER_0_Config, /* spi master configuration structure pointer */
.runtime = &SPI_MASTER_0_runtime,
};
/*
* @brief Configure the port registers and data input registers of SPI channel
*
* @param[in] handle Pointer to an object of SPI_MASTER configuration
*/
static SPI_MASTER_STATUS_t SPI_MASTER_0_lInit(void)
{
SPI_MASTER_STATUS_t status;
status = SPI_MASTER_STATUS_SUCCESS; // TODO: remove status
/* LLD initialization */
XMC_SPI_CH_Init(XMC_SPI2_CH1, &SPI_MASTER_0_Channel_Config);
XMC_SPI_CH_DisableFEM(XMC_SPI2_CH1);
XMC_SPI_CH_SetBitOrderMsbFirst(XMC_SPI2_CH1);
XMC_SPI_CH_SetWordLength(XMC_SPI2_CH1, (uint8_t)8);
XMC_SPI_CH_SetFrameLength(XMC_SPI2_CH1, (uint8_t)64);
/* Configure the clock polarity and clock delay */
XMC_SPI_CH_ConfigureShiftClockOutput(XMC_SPI2_CH1,
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK);
/* Configure Leading/Trailing delay */
XMC_SPI_CH_SetSlaveSelectDelay(XMC_SPI2_CH1, 2U);
/* Configure the input pin properties */
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT4_BASE, (uint8_t)6, &SPI_MASTER_0_MISO_Config.port_config);
/* Configure the data input line selected */
XMC_SPI_CH_SetInputSource(XMC_SPI2_CH1, XMC_SPI_CH_INPUT_DIN0, (uint8_t)SPI_MASTER_INPUT_E);
/* Start the SPI_Channel */
XMC_SPI_CH_Start(XMC_SPI2_CH1);
/* Configure the output pin properties */
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT4_BASE, (uint8_t)7, &SPI_MASTER_0_MOSI_Config.port_config);
/* Initialize SPI SCLK out pin */
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT4_BASE, (uint8_t)2, &SPI_MASTER_0_SCLKOUT_Config.port_config);
/* Configure the pin properties */
XMC_GPIO_Init((XMC_GPIO_PORT_t *)PORT4_BASE, (uint8_t)3, &SPI_MASTER_0_SS_0_Config.port_config);
XMC_SPI_CH_EnableSlaveSelect(XMC_SPI2_CH1, XMC_SPI_CH_SLAVE_SELECT_2);
XMC_USIC_CH_SetInterruptNodePointer(XMC_SPI2_CH1,
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
(uint32_t)SPI_MASTER_SR_ID_0);
return status;
}
↧
September 4, 2018, 8:21 pm
↧
September 5, 2018, 1:33 am
Below are osci shots with low speed 76800 Baud (working) and higher speed 115200 Baud (not working). It seems the XMC has some auto-chip select feature, which kicks in with higher speeds and de-selects the device.
The transfer is sending 4 bytes (0x9e 0xFF 0xFF 0xFF), so you can see 32 clock cycles (
blue). The
violet signal is chip select, the
yellow one the XMC MISO.
76800 Baud:
Attachment 3596
115200 Baud de-selects after the first byte (0x9E), then keeps chip selected until all 3 bytes have been received.
Attachment 3597
Can anyone point me into the correct direction?
Thanks,
Ernie
↧
↧
September 5, 2018, 2:33 am
The problem was in configuration routine. Following line
Code:
XMC_SPI_CH_DisableFEM(XMC_SPI2_CH1);
needs to be replaced by
Code:
XMC_SPI_CH_EnableFEM(XMC_SPI_CH_EnableFEM);
To set "Frame End Mode" to 1, which prevents the XMC from de-selecting the CS line if TDV (transmit register) runs empty.
Case closed.
↧
September 5, 2018, 7:43 am
Hi all. I found the documentation of the Step C of the GTM VRS Engine position driver but only the example code of the Step A. Has someone any idea of where can I find the Step C code?
Thanks,
GB
↧
September 5, 2018, 8:05 am
Hello,
I try to implement a gateway with FIFO on a TC277 but I encounter a problem.
I have set MO10 to receive a CAN frame on CAN 0 and transmit it to the CAN 1 using a FIFO with MO4, 5 and 6.
I set MOFGPR10 with SEL =0, CUR= 4, TOP= 6 and BOT = 4.
MOFCR10 is set in Gateway mode
MO4, 5 and 6 are set as FIFO slave with CUR = 10, TOP =6 and BOT = 4.
TXEN1 is set to 1 in MO 4
The first 3 frames are transmitted, TXEN1 is sent in MO5 after the first Tx then set in MO6 after the 2nd but after it doesn't roll to MO4 and none of the 3 MO have a TXEN1 set to 1.
I have check MULTICAN_CONFIG_EXAMPLE_XMC47 but it use DAVE to configure the Message Objects so I can't check the registers value.
Any idea about what is wrong ?
↧
September 5, 2018, 9:45 am
↧
↧
September 5, 2018, 12:43 pm
I want to buy a printer which will help to print the study materials. From
outlook support, I get various kinds of the printer.
I can't take the proper decision which one should I buy for the study purpose?
↧
September 5, 2018, 7:55 pm
hi Andi, can you also email to me the example for DS18B20. Im currently using xmc1400 boot kit. Will it be compatible with xmc1400?
thank you
↧
September 6, 2018, 3:52 am
Hi there!
I have a TLE9180D 3 phase bridge driver in communication with an Aurix TC234. I followed the power-up sequence of the bridge driver, and everything seems to be fine.
All the error flags are 0, and the PWM signal applied on the digital inputs are shown at the output level. The operation Mode is "normal" (Om_over == 0x80).
I have a VADC sample at the 10kHz PWM signal edge. The gain of the current sense amplifiers is 30.81, the VRO voltage level is 2.5V. When no current flows, I see the expected values, and I can measure
the expected 2.5V at the VOx outputs.
Here comes the non-sense:
When I apply a differential voltage at the shunt terminal, and there is current on that resistor (with switching power supply in current limiting mode), I cannot see any changes in the output voltage.
Does not matter, how many amps are flowing through the shunt resistor, the amplifier output is at 2.5 Volts, which is the zero current voltage.
All the current sense amplifiers are enabled, and there is no break on the hardware.
The output of the differential amplifiers are zero bacause of an unknown reason.
Thank you for the answer!
↧
September 6, 2018, 4:24 am
Hi
1. Not able to flash into TC277TF board using UAD pro 2 debugger
Attachment 3598
PFA of the failure report
What is the issue?
2.Can i get the bootmode header for flashing into the Tricore Tc277Tf controller
↧
↧
September 6, 2018, 5:00 am
DAVE Webcast - Getting started (see DAVE4 project attachment)
Install DAVE IDE for XMC microcontrollers
1. Browse to
DAVE software download
2. Register and select the DAVE package you would like to download depending on your operating system.
3. To install DAVE, all you do is unpacking the downloaded zip file to a location of your choice (i.e. c:\DAVE4).
Quote:
Note
For Windows, a number of problems have been reported when people try to use Windows Explorer to unzip the zip file. Please use a third-party unzip program, such as 7-Zip
4. To simplify starting DAVE4 in the future, create a shortcut on your desktop to the DAVE.exe file in the eclipse folder.
5. Download and install the J-Link Software and Documentation pack for Windows.
6. Start DAVE by double clicking the shortcut to Eclipse that you just created above.
The following splash screen will appear
Attachment 3600
and then an Eclipse Launcher pop-up window will appear.
Attachment 3601
Click OK.
More information about DAVE can be found in the
Quick Start Guide
↧
September 7, 2018, 7:55 am
Hello,
I have measured the execution time of my program using:
1) Software cycle measurement followed by division of clock frequency --> #cycles / f_clk
2) Counting Ticks in the MCDS trace viewer (column "Ticks" or "TimeR") --> (#ticks*2) / f_clk (ticks*2 as 1 tick = 2 cpu clock cycles)
3) Direct time measurement in MCDS (column "TimeA" which shows the accumulated time in nanoseconds)
2) and 3) seem to be approximately the same, but 1) says that my program runs a lot faster.
Example: 1) measures
20,46059 ms - 2) measures
35,32313 ms and 3) measures
35,51473 ms
in the software cycle measurement, I read out the clock frequency of the CPU by a given function from Infineon which returns 100MHz in my case (after reset)
the MCDS Trace Viewer shows me the Message, that it uses 100,8MHz as frequency.
Attachment 3605
I have checked twice, if i programmed the same .hex file for the different measurements.
↧
September 7, 2018, 1:46 pm
Hi, is there any updates from Infineon regarding this matter? We are trying to update the SII in the eeprom and ran into some problems. I guess if the EEPROM reload and write is not setup in MainInit, the SII will not be updated?
↧
September 10, 2018, 12:59 pm
Hi,
Please have a look to the ERU_EXTINT example in the
XMCLib distribution.
Regards,
Jesus
↧
↧
September 10, 2018, 11:49 pm
↧
September 11, 2018, 1:33 am
Hello,
I tried to assign a hotkey (F8) to the Main Menu item "Project -> Build", but it doesn't work.
Is there any other way than using "Window" -> "Preferences" -> "General" -> "Keys" -> "Build Project" -> "Binding"? It seems that the "When" is not matching.
Best regards,
Ernie T.
↧
September 11, 2018, 1:33 am
I'm facing some strange behavior when implementing timer interrupts on the XMC1100 (XMC1100T016X0064)
Using DAVE, I selected a Manchester decoder on Slice 0, and a 1 millisecond timer on slice 1.
All seemed to work ok, until I started investigating some strange behaviour.
First I discovered that the interrupt priority was not behaving as expected.
The Manchester decoder interrupt was executing at lower priority than set. It was interrupted by an low priority interrupt which I found strange.
I checked every configuration register using the debugger and all seemed correct to me. (Slice 0 was set to 0, others to higher values (lower prio))
By pure luck I discovered that setting the priority for Slice 0 to Slice 1 solved the issue.
After digging deeper I found that Slice 0 triggers the interrupt handler/vector for slice 1 (CCU40_1_IRQHandler ; Handler name for SR CCU40_1)
and vice versa Slice 1 triggers interrupt for slice 0 (CCU40_0_IRQHandler ; Handler name for SR CCU40_0)
I was puzzled. How could my application ever have worked? I checked the Errata sheet but I was unable to find any information regarding this behaviour.
Then I discovered DAVE apparently knows about this because it "compensates" by generating the following macros:
#define MANCHESTERCoder_CCU4IRQHandler IRQ_Hdlr_22, which links the Manchester decoding library (Hardcoded to slice 0) to the interrupt handler of Slice 1
and
#define TIMER1_ISR IRQ_Hdlr_21, which links slice 0 interrupt to the slice 1 handler.
Questions:
- Is this a known issue?
- If it is, why isn't it in the Errata sheet?
- If it isn't why is DAVE compensating for this?
- Why are the interrupt priorities not switched for Slice 0 and 1 in the initialization code?
↧