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[Position2Go Kit] Unable to flash using XMC Flasher

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Hi there,

XMC Flasher version 1.1.1.201905161342
Position2Go HW version 1.2
I get this error when I try to connect to XMC4700-2048, "Please first connect an emulator!".
I have both usb ports connected, any idea what else I could be doing wrong here? Do I need to install XMC serial drivers ?

Programming spec for XDPE10280

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Hi Sir,

Good day.

Recently our customer requires the programming support for XDPE10280.
We will develop a tool on our programming platform for production. Could you help to provide the programming guide/spec. for develpment?
Please let me know if need to sign NDA. Thank you.

Put some variables into External SDRAM with XMC4800 from Automation Board

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Guys! Right now I am facing a very hard challenge. I have asked two questions here, apparently, no one responded to me.

The Questions I post here:

1. How to use UART debug trace in XMC4800 Automation V2 Board

2. My XMC4800 board with the Ethcat slave function always runs exceptionally

My main problem is the second one, and the UART debug issue is the debug solution I want to use. But the Automation Board V2 don't wire the related pins from XMC4800.

To overcome the main problem, I think my const arrays are too many, I decided to use the external SDRAM available in Automation Board.

I referenced the EBU SDRAM source code from : https://es.technikum-wien.at/bel/bel.../EBU/EBU_SDRAM

Then I wrapped the initialization source code like below:

Code:

__WEAK void init_sdram_component()
{
    /* EBU Clock is divided by 2 - To program the divider connecting a parent and its child clock node*/
    XMC_SCU_CLOCK_SetEbuClockDivider(2U);

    /* Enable EBU Clock */
    XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_EBU);

    EBU_MUX_Init();
    EBU_Init();
}

Then call this function in SystemInit from system_XMC4800.c, I put it into the end of the SystemInit like below:

Code:

__WEAK void SystemInit(void)
{
  delay(10000000);
  memcpy(g_chipid, CHIPID_LOC, 16);

  SystemCoreSetup();
  SystemCoreClockSetup();
  init_sdram_component();
}

I also modified the linker_script.ld, the attachment is the link script, and I make a summary of my changes:

Code:

MEMORY
{
  FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x00200000
  FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x00200000
  PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000
  DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000
  DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000
  SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000
  DSRAM_3_external(!RX) : ORIGIN = 0x60000000, LENGTH = 0x4000000
}

The bold line is my adding, then I added 3 new sections:

Code:

SDRAM_RODATA :
  {
    . = ALIGN(4); /* section size must be multiply of 4 */       
    __sdram_rodata_start = .;
    *(SDRAM_RODATA)
    . = ALIGN(4); /* section size must be multiply of 4 */
    __sdram_rodata_end = .;
  }  > FLASH_1_cached AT > DSRAM_3_external

  SDRAM_BSS :
  {
    . = ALIGN(4); /* section size must be multiply of 4 */       
    __sdram_bss_start = .;
    *(SDRAM_BSS)
    . = ALIGN(4); /* section size must be multiply of 4 */
    __sdram_bss_end = .;
  }  > DSRAM_3_external AT > DSRAM_3_external
 
  SDRAM_DATA :
  {
    . = ALIGN(4); /* section size must be multiply of 4 */       
    __sdram_data_start = .;
    *(SDRAM_DATA)
    . = ALIGN(4); /* section size must be multiply of 4 */
    __sdram_data_end = .;
  }  > DSRAM_3_external AT > DSRAM_3_external

Finally, I put attribute statements before any global variables that I strongly suspect like below:

Code:

__attribute__((section("SDRAM_BSS")))
static Control_Block _earth_control_block;

/* PDOs and their contents: */
__attribute__((section("SDRAM_RODATA")))
static const ESS_PDO_ENTRY PDO1600Entries[] = {
    { 0x7040, 1, 1 },
    { 0x7040, 2, 1 },
    { 0x7040, 3, 1 },
    { 0x7040, 4, 1 },
    { 0x7040, 5, 1 },
    { 0x7040, 6, 1 },
    { 0x7040, 7, 1 },
    { 0x7040, 8, 1 },
    { 0x8000, 0, 8 },  //xsafety control byte
    { 0x8001, 0, 8 },  //A1 control byte
    { 0x8002, 0, 32 }, //A1 demanded current
    { 0x8011, 0, 8 },  //A2 control byte
    { 0x8012, 0, 32 }, //A2 demanded current
    { 0x8021, 0, 8 },  //A3 control byte
    { 0x8022, 0, 32 }, //A3 demanded current
    { 0x8031, 0, 8 },  //A4 control byte
    { 0x8032, 0, 32 }, //A4 demanded current
  };

Unfortunately, the main problem is still existing, I am begging you guys to help me to analyze the root cause from my whole story?

Thanks!

EEPROM Emulation Problem XMC4200

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Hi,

we have encountered problems related to the EEPROM emulation of the XMC4200.

1. When changing from one 16k block to the next 16k block, the old 16k block is erased during the next start of the firmware (reset or power cycle). If this is done during a power cycle, erasing could fail due to bouncing of supply (which can never be avoided). If this bouncing occurs, the flash gets into the following state:
- the sector used for EE emulation (64k starting at 0x08010000) is cleared completely to zeros
- the sector can no longer be written (tested with SEGGER J-Link Commander and with the firmware)
- other parts of the flash above 0x08030000 can be written (tested with SEGGER J-Link Commander)
- the EE flash emulation sector can be written after the chip has been erased completely (SEGGER J-Link Commander command "erase")
We got several chips into this state (~7 out of 50). We are going to fix the problem by rewriting the EE emulation code such, that it erases the flash immediately after it has been written.

2. The code, that checks the VERIFY error bit in the flash status register FSR checks using the equality operator which is wrong in my opinion. Shouldn't this be done using the AND operator? This check should return an error, when the chip got into the state described above, but it returns success, because a second bit number 4 called PROG is set too.

Anyone else got this kind of problems?
What state could the flash sector be in (point #1 above)?
Is this a "logical / physical sector issue"? How are they related to each other? Are they really separate or can clearing a logical sector clear the whole physical sector accidentally?
Why is the clearing of the flash delegated to the next bootup of the firmware instead of doing it immediately?

AURIX TC29x Flash Setting

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Quote:

Originally Posted by jie_xu View Post
And this is the hex file

:0200000480007A
:2000000000000000700059B30000000000000000000000000 000000064B81E799B47E18668
...

The hex file is writing on the Flash memory of your device, thus if the program does not work "without using PC" you have a problem in the code.

Does the program works when started from the AURIX™ Development Studio in debug mode?

BR,
teoBits

iLLD in Aurix sample code on github

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Dear teoBits

Thank you for your reply.
Can these iLLDs be used freely? Is there any licensing? What are the terms for using them?

Best regards
Shailendra

AURIX TC2X7 Development Board programming

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Hi, where did you find the LCD Demo ? I tried looking on myInfineon but i didn't find anything. Thank You

Period of Fault Signaling Protocol [SMU_FSP] during Fault Free State

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Hell Support,
For Aurix 2G devices, In the revision 1.4 User Manual Part 1, there is
"Figure 167 Time switching protocol"
related to SMU Fault Signaling Protocol.

In the above mentioned figure, Tsmu_ffs [Period of 50% waveform] is determined by "TFSP_HIGH & TFSP_LOW" field value of SMU_FSR Register.
Is the correct statement?

or "TFSP_HIGH & TFSP_LOW" value determines Tsmu_ffs /2 [that means the high duration of the waveform]?

Which one is the correct statement above?

"TFSP_HIGH & TFSP_LOW" -- means concatenated total value of fBack/PRE2 clock ticks. I am assuming this is correct.

Best Regards

SMU Alarm Status Register doesn't reset on Target Reset for Aurix 2G

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Hello Support,

According to User Manual Revision 1.4 for Aurix 2G, SMU_AGi [0-11] -- SMU Alarm Status Registers [Offset 1C0H+i*4] are supposed to be cleared to zero upon Application Reset.
Can you please confirm whether these registers are indeed cleared upon Application Reset/Lauterbach Target Reset?
For my Triboard, I see AG0/AG1/AG2/AG3 as 0x2490 upon Target Reset.
Best Regards

FAQ for miscellaneous ePower Topics

IMC301A usart connection problem

TC399 Ethernet Problem

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iLLD example for TC3xx configures the PHY as loop back mode, so no frames get out, to fix this disable loopback mode and comment
portions of the code that is waiting for the received frame (demo expects to receive the tx frame)

Can't set BMI back after change to CAN_BSL

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Hello all,

I am new to ARM microcontrollers and XMC in particular. I am working with the XMC1403 with DAVE and J-Link Lite through SWD0 without issues so far. I have been able to change the BMI from ASC to SWD0 without problems.

But I will want to use CAN_BSL eventually and I have changed the BMI to it and I can't make it work. I don't see the ACK frame but this is another issue. Is it possible to set back now the BMI to ASC or SWD0? Now I can't communicate. Is this normal? I don't have the wires but via ASC would it work? Do I need another tool?

Thanks

XMC BOOT Kit user manual

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Dear Infineon
An user manual should have all informations needed to "USE" the "thing" for which that manual was written.


I am a newbie to XMC. So I bought an XMC boot kit (XMC1300)
At page 9 form " Board_Users_Manual_XMC1300_CPU_Card_R2.pdf " there is a word about "Debug connector X201 "
Where is this connector located on the board? There is no silkscreen with parts references/designators on pcb. You did not supplied an assembly drawing with parts designators on the PCB (you only show the schematic and pcb copper layer)

How about the DIP switch ? What does it do?
And I just started to browse the manual...

BLDC_SHIELD_TLE9879 questions.

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Quote:

Originally Posted by Elettrograffiti View Post
how many bits is this encoder? If it is just 3, line an Hall sensor, you could try to use the hall pattern detection to your advantage. Otherwise you could use any GPIO in input mode and generate interrupt function for your loop regulation.

It's AB incremental encoder. Some microcontrollers, like STM32 have a timer that may be configured as AB encoder reader. You say I can set two pins as inputs and decode it on pin interrupt?

Potential errata in Infineon SLB9670 Trusted Platform Module

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I am using a SLB9670 TPM (Vendor String: 7.40.2098) module to create a duplicate of a key generated in that same TPM, for the sake of clarity:

- TPM_A: The TPM where I created a key.
- TPM_A_KEY: The key generated in TPM_A that I want to create a duplicate of.
- TPM_B: The TPM where I want to import the duplicate.
- TPM_B_KEY: The ECC P-256 key generated in TPM_B which I want to use to wrap the duplicate create in TPM_A of TPM_A_KEY.

As part of this process, I need to import the public part of TPM_B_KEY in TPM_A, for which I use the LoadExternal TPM command, which allows me to load the external public part (TPM2B_PUBLIC), the private part is set to the empty buffer, TPM_B_KEY has the attributes DECRYPT and RESTRICTED.

In the SLB9670 Module I am unable to do this, I receive a 0x101 error (TPM_RC_FAILURE) and the TPM enters into Failure Mode, unable to process any other commands. In the SLM9670 it works OK, same for Microsoft TPM Simulator, I do not receive any other errors. The TPM2B_PUBLIC structure has no errros, it contains the symmetric algo for wrapping, the public components X and Y...

I am using a HMAC session for the command, but without a session it is also possible to reproduce.

I have also noticed that I am able to import keys with SIGN as the only attribute, but if I try to load it with a session it enters into Failure Mode.

I am able to create the duplicate successfully, import it... with the Microsoft TPM Simulator and also with the SLM9670 (Vendor String: 13.11.4555) module, without any changes in the code.

This all seems quite strange, so I am thinking that perhaps this is an errata or undefined behaviour in the SLB9670 chip, and I was wondering if someone at Infineon would be able to look at this. I can provide TCTI communication traces if required, but I think it should be easy to reproduce, just call LoadExternal with a decrypt/restrict ECC NIST P256 key.

Many thanks for your help.

SDRAM on EBU with XMC4700 using P5_8 as Clock

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Update: If I connect P5_8 as clock and define P6_4 as clock too ( without connecting it to sdram) all works without problem.

The waveform on P5_8 and P6_4 are the same...

Luca75

SCU_STCON Register STP Bit for Aurix 2G

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Hello Support,

In the AURIX 2G, there is a register SCU_STCON -- Start-up Configuration Register -- Offset 0xC4.
Bit 15 is STP.

Following sentences are in the User Manual Part 1 Revision 1.4 for STP bit

"
This bit will be always set by FW and can't be reset.
This bit is also cleared by an Application Reset.
STP is automatically set when a shutdown trap occurs.
"
1>
Looks like STP is cleared when Application Reset but during Cold Power On Reset it will be SET.
Is that correct?

2>
FW -- means Boot_ROM Firmware which is SSW
Is that correct?

3>
Can you please point me to documentation regarding "shutdown trap" as mentioned above?

Best Regards

Aurix 2G SMU Alarm Clear process at Power On Reset

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Hello Support,

For Aurix 2G Part 1 User Manual Revision 1.4 there is the following section as table as mentioned below:

Section -- 15.3.1.5.4 Alarm Status Registers
Table 530 Handling of Alarm Status

There is a mention of ALARM[I] signal for every AG<x>[I] register within the Table 530.
Can you please tell me which register bits ALARM[I] maps to?

Attachment 4634

Best Regards
?????

CPUx put CPUx in IDLE

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Hi cwunder,

Currently the driver what I have is based on AUTOSAR. So I couldn't find some functions from your code snippet..
If you tell me where the following functions are located (filename), that would be helpful.
function names: IfxCpu_enableInterrupts, IfxCpu_emitEvent, IfxCpu_waitEvent, IfxScuWdt_clearCpuEndinit.

Could you also tell me the driver name and version, that you have used in your code snippet?

Thanks!
Siva.
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