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The issue about QSPI communication with TFT

November 13, 2020, 10:48 pm
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Hello, everyone.

I have tried to work TFT lcd on TC237 app-kit since 2 weeks ago.
I have used the demo code for TC237 app-kit which is provided from infineon.
It has worked well. but I only wanna extract the code for operating TFT because of My project.
So, I have tried to extract TFT function codes from the demo files.

However, My TFT has displayed continuous thin black lines like below.
I copied and pasted this exact same codes on new project for TFT test.
I think it has QSPI communication problems by unknown errors. but I have exactly copied the TFT code work-well .

Please give me your opinion about this problem.
How can I solve this problem?

Attachment 5278
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DPS310 pressure data

November 14, 2020, 3:09 am
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Hello,
I have a DPS310 eval board connected to an ANALOG2 DISCOVERY tool to generate SPI frames.
I've not been able to get correct temperature and pressure data.
I set the correct TMP_EXT bit in TMP_CFG register to 1 as per what is in Coefficient Source register bit 7 and now I have a much better temperature value
at least coresponding to what it should be around 20°C.
But the pressure is still too low.
My registers are set as follow:
0x06 = 0x14 : PM_RATE= 1 or 2 measuremetn/sec and PM_PRC=4 or x16 oversampling rate
0x07 = 0x90 : TMP_EXT=1 and TMP_RATE=1 or 2 measurements/sec and TMP_PRC=0 (no ovesampling)
0x09 = 0x07 : permanent pressure and temperature measurement enabled
I used for pressure the kP=253952 and for temperature kT=524288
atmospheric pressure is supposed to be 1015hPa now and here. I get only 736.85hPa.
I do think that my coefficients are correct and I two's complemented. Same for pressure raw data.

Do you have an idea where the problem lies? I attached my excel sheet that you used to calculate my pressure and temp.

thanks for your help.

Alain
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IDWD40G120C5 PSpice Model Error

November 14, 2020, 3:22 pm
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I am getting an error when using the PSpice model of the IDWD40G120C5. When I use the ideal diode instead of the model in the circuit, there is no error. PSpice defines the error as "There are no data values in section number 1. Ignoring this section". I would like to ask for your help as I will carry out this circuit for my master thesis.
Attachment 5281
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Aurix Microcontroller TC277TP, internal capacitors

November 15, 2020, 8:24 pm
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Hello, I'm using "TC277TP" Aurix controller with 20M Hz external oscillator. Now i want to remove external load capacitances of oscillator and use internal capacitors at XTAL1 & XTAL2 pins.
How internal capacitors are connected at XTAL pins, is it possible to use them as load capacitance for external crystal oscillators?

Thanks in advance
Srikanth
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IR11672ASPBF, after the EN pin is turned off, how is the output going be?

November 16, 2020, 1:06 am
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IR11672ASPBF, after the EN pin is turned off, the output is floating, high impedance, low?

Hello, everyone,

I am currently designing IR11672ASPBF for ACDC rectification applications. I have a question:

After the EN enable pin is turned off, what is the output state of the chip, floating, high impedance, and low? The manual did not see the details.

thank you very much!
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How to do special error handling with multiple LITIX™ Basic+ devices?

November 16, 2020, 6:31 am
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Exceptional error handlings when having multiple devices, e.g. for TAIL/STOP applications, can be implemented with LITIX™ Basic+. This is useful if the light function, where the error occurs, determines which LED driver to turn off and which LED driver to keep on. For example if the LEDs of the TAIL light have an error, only the TAIL light may be turned off and the STOP light may be kept on. On the other hand, if the LEDs of the STOP light fails, all STOP and TAIL shall be turned off.
There are two solutions:

Solution 1:
Connect the ERRN node of the Tail/Stop part to the enable circuit of the Tail part:
Attachment 5283

Due to the voltage thresholds of the EN/DEN pin (the lowest is 1.4V) there is some margin.
Advantage here is that the devices disabled via EN/DEN consume almost no current (<2µA)
This can be used in case no additional turn off delay via a capacitor at the D-pin is required.

Solution 2:
The ERRN network needs to be split by a diode and place RERRN pull up resistors on either side of the diode:
Attachment 5282


The resistors and diode have to be designed such that the voltage VERRN goes below 0.8V in an error case. Therefore one also needs to consider the forward voltage of the diode because a small current (e.g. 0.5-1mA) is flowing through it. The remaining ERRN voltage of the device pulling down the node is also depending on the current which is flowing into it. A Schottky diode is beneficial due to the low voltage drop.
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How to power up DC-DC converters with TLD509x boost control ICs?

November 16, 2020, 9:18 am
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LITIX Power devices are using FBH pin for short-to-ground detection and current sensing. The DC-DC converter will not start up as long as the voltage at FBH is below 2V.

Some topologies like boost to ground the voltage at FBH automatically rises above 2V at FBH when an input voltage is applied when the LEDs are directly connected to the output capacitor. Therefore the DC-DC automatically and quickly starts.

When having topologies like SEPIC or when having a dimming switch at the LEDs, the voltage at FBH has to be pre-biased (e.g. by a diode Dpol and a resistor Rpol from IVCC to FBH - see application diagrams in the datasheet). Then the power up time depends on the time constant of Rpol and the output capacitance Cout. The power up time can be minimised by minimizing Rpol. However, this is limited by the maximum output current at pin IVCC.

Take a look at the LITIX Power page for more information
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Mcal – atom

November 16, 2020, 12:58 pm
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2nd Attempt

Dear Community Members,

Any help on this topic !!!
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Dealing with a "crash" with FreeRTOS

November 16, 2020, 1:24 pm
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Hi ,

I have and are using the StateViewer plugin. Everything looks good.
I was testing with the Watchdog and set a breakpoint in the Handler.
I noticed a similar stack trace as above. The "<signal handler called > () at 0xfffffd"
Doesn't FreeRTOS use a different stack for each Task?
What I posted above, does that imply that I got a interrupt or an errant interrupt?
Do I somehow have a interrupt with no defined Handler?
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Aurix 2G Peripheral Module Wait State Values

November 16, 2020, 2:10 pm
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STM, PSI5, PSI5S, HSSL, HSCT: 1 additional wait state
DMA, ERAY, I2C: 2
GETH - 4
EVADC-8
EDSADC -8
CONVCTRL-8
MTU(SSH) - 9
GTM - 9
PMS - 8
Peripherals not listed above: 1 SPB wait state
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GTM: TOM: Two independant Phase shift output from TOM channels

November 16, 2020, 11:01 pm
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Quote:
Originally Posted by arshadziyad View Post
Is it possible to generate two indepdendant phase shift outputs from channel 1 and channel 2 w.r.t to master output signal on channel 0 in the same TOM unit.
All the outputs should have duty cycle and period and difference is in different phase shift (phase 1) of channel1 and (phase 2) channel 2 w.r.t to master signal on channel 0.
Yes, it is possible to use one timer as master and others as slaves. The period would be synchronized by using the reset signal of the master for the slaves as well.
You need to calculate the phase shift in software, either on CPU or maybe also in MCS.
One idea could be to set the PWM channels to inactive LOW via SL bit and configure the required duty cycle (for the HIGH duration).
The output will be set to LOW again after the timer has reached it's maximum and the reset from master timer restarts the PWM channel.
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How to clear SMU Alarm 7[1] and Alarm 7[4]

November 17, 2020, 12:25 am
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Also, you could write to SMU.AG7.SF1/SF4 to clear the status flags for these alarms.
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Looking for the XC164CM UCAN Starter kit USB stick

November 17, 2020, 12:31 am
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What is the recommended capacitive OUT filtering for LITIX Basic products?

November 17, 2020, 2:23 am
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For all LITIX Basic variants with "Open Load" detection functions the following recommendation applies:
LITIX Basic ICs with integrated Open Load functions require a capacitive divider on the OUT. This means CVS2OUT and COUT2GND should be implemented to achieve a robust EMC design. This has been evaluated during our EMC investigations. The reason for this is to increase filter capacitance on the OUT. If it is only done via increasing the COUT2GND capacitor, the open load detection is not working properly anymore. To avoid this the CVS2GND has been recommended as well.

For all LITIX BASIC ICs without the "Open Load" detection function implemented the following recommendation applies:
LITIX Basic products without Open Load detection functions such as TLD1120 do can skip the CVS2OUT capacitor.
The GND connection of the LED load can cause a parasitic behavior during the BCI test. The layout of the PCB Board design is also an important factor how many disturbances the IC OUT or in this case the current regulation loop of the IC will see during the BCI test. The COUT2GND will filter eventual disturbances and ensure a more stable output current regulation.
NOTE: The actual datasheet drawing of the TLD1120 is showing a CVS2OUT capacitor only! This may not solve BCI issues and a COUT2GND filter is recommended.

See also the LITIX Basic page and in particular the corresponding application note
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How can I use the TFT LCD in Application board TC237?

November 17, 2020, 6:54 am
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Quote:
Originally Posted by CookieMonster112 View Post
If you want to use the TFT display code, you would need to extract it from the package.
@CookieMonster112

Thank you for your reply.
Yes, I finally built the demo code through the another positing which have been posted on this site.
(It is the positing that how to build the BIFACE project with AURIX IDE.)
So, My TFT on TC237 app-kit has worked well.

But I only wanna extract the code for operating TFT because of My project.
So, I have tried to extract TFT function codes from the demo files.
However, My TFT has displayed continuous thin vertical black lines like below.
I copied and pasted this exact same codes on new project for TFT test.
I think it has QSPI communication problems by unknown errors. but I have exactly copied the TFT code work-well .

Please give me your opinion about this problem.
How can I solve this problem?

Attachment 5286
?????
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Can I use LITIX POWER LED drivers when applying PWM via switched power lines?

November 17, 2020, 8:14 am
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Yes, LITIX Power products can be used when the power lines are being switched. Please consider that the enable pin EN / PWMI receives the correct PWM signal - and not a distorted signal after the input filter. See this application note for more details and take a look at the LITIX Power page..
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HOST and HSM accessing Their D Flashs Simultaneously on TC39x

November 17, 2020, 8:41 am
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ECC errors in DFLASH do not cause a bus error. Instead, read errors are reported via HF_ECCS (for DF0) and SF_ECCS (for DF1).

What is causing the reset? Is there an SMU alarm? Is there a CPU trap? Can you also check DEADD?
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Endless active error frames on CAN bus by XMC4500 node

November 18, 2020, 12:46 am
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iLLD and PXROS-HR

November 18, 2020, 12:50 am
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Hello *,

We are developing a safety-critical application (IEC61508 - SIL2) using both the toolchain and the PXROS-HR operating system provided by Hightec on a Infineon AURIX TC299 device.
According to PXROS-HR implementation guidelines, interrupts should never be disabled in the FW application. But, we are also used your iLLD, which in turn foreseen the disabling of interrupts.
May this bring to conflicts? An how can we be sure that the iLLD functions we are using do not disable Interrupts (i.e. can we simply empty functions "IfxCpu_disableInterrupts" and "IfxCpu_enableInterrupts")?

Many thanks,
Marco Rona
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TC275: Can't clear ALM 2[7] (PFLASH ECC monitor)

November 18, 2020, 2:36 am
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Hello all,

I can't clear ALM 2[7] (PFLASH ECC monitor).

It's failing inside the PmuEccEdcTst.c (Aurix SafeTlib). One of the test steps attempts to clear all SMU alarms and this is failing fails because AL2[7] is still set.

I've enabled CBAB & UBAB monitoring with the debugger and executed the alarm clear code. There are no valid entries but AML 2[7] is still set after the clearing of the alarms.

Does anyone know how I can I work out why the alarm is continually active?

Regards,

Mark.
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