I just download the latest DAVE version, and libraries. When I try to debug the example application UART_EXAMPLE_XMC45 in my XMC 4500 i get the following error :
Anyone can help?
Anyone can help?
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DAVE 4 debug error: error in services launch sequence
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Sample programs (Beginner programs) for AURIX TC27x
Quote:
Originally Posted by TASKING.hp.glas
![View Post]()
Also available from here are the AURIX Book Examples; an extensive set of examples, recently ported to TC277 D-step.
Henk-Piet Glas
Technical Product Specialist
where exactly can I find this AURIX Book Examples?
I've installed the SW Framework but can't find any examples there.
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Ref. manual of XMC 4800: How set up digital input (e.g. button1 - P15.13) ?
Hello,
For Port 14 and 15 pins which has both analog and digital input functions, both the corresponding IOCR and PDISC bit fields need to be configured.
For example, to enable the digital input function for P15.13:
Note that the above will be automatically taken care of when using the XMC Lib function XMC_GPIO_Init() or DAVE DIGITAL_IO app.
Regards,
Min Wei
For Port 14 and 15 pins which has both analog and digital input functions, both the corresponding IOCR and PDISC bit fields need to be configured.
For example, to enable the digital input function for P15.13:
Code:
/* Configure P15.13 for direct input with no pulls */
PORT15->IOCR12 &= 0xFFFF07FF;
/* Enable digital input for P15.13 */
PORT15->PDISC &= 0xDFFF;Regards,
Min Wei
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Get active on XMC, DAVE Forums and Be Rewarded!
Reminder...
The 1st Apple Watch winner will be announced in May!
Attachment 2263
Get moving and get your user points and reputation up.
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We will contact the winner via email shortly. Check your mailbox! :)
The 1st Apple Watch winner will be announced in May!
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How to code in c++ and c with DAVE
:) good to hear that.
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CPUy setting CPUx into Idle - AURIX TC29X
I would like to ask if someone has experience in using Infineon's IfxCpu_setCoreMode API function (In IfxCpu.c) to place a CPU into Idle mode by another CPU?
Calling IfxCpu_setCoreMode(&MODULE_CPU0, IfxCpu_CoreMode_idle); from CPU1 causes CPU0 to reset instead of placing it in Idle.
Any help would be much appreciated.
Calling IfxCpu_setCoreMode(&MODULE_CPU0, IfxCpu_CoreMode_idle); from CPU1 causes CPU0 to reset instead of placing it in Idle.
Any help would be much appreciated.
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Communication problem in UART
Are both micros powered by the same rail supply? If the VCC of one micro rises faster than the VCC of the other micro, the micro with the slower VCC can get latched up.
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External RAM on TriCore
Hi,
We are considering the TriCore TC29x for one of our upcoming products. It will be used in an application where we will need access to external RAM.
Do any of the TriCore processors support external RAM? I don't see it explicitly mentioned anywhere in the datasheets, but it is looking like external RAM is not supported.
Thanks,
Nick
We are considering the TriCore TC29x for one of our upcoming products. It will be used in an application where we will need access to external RAM.
Do any of the TriCore processors support external RAM? I don't see it explicitly mentioned anywhere in the datasheets, but it is looking like external RAM is not supported.
Thanks,
Nick
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USB overwriting data array
I am using ADCSYNC to sample 4 channels simultaneously. The adc fills up 4 arrays which is subsequently transmitted to a host pc over USB upon reaching a predefined number of samples. Before USB transmission is initiated the sampling interrupt is stopped.
It seems, however, that somehow the USB is writing to a certain memory address which is also contained in one of my data arrays, and I loose that particular data.
The problem occurs at the same address every time (word at 0x20000CD0). Using the debugger I could assert that the data is sampled correctly, but when the code proceeds to USB tasks the particular memory is overwritten before being transmitted to the host.
I cannot identify the precise command that is responsible for the write operation, but I am convinced that is the usb - watchpoint does not pick it up???
The above happens with the USBD_VCOM app on the XMC4400.
When I try to use the old app (USBVC001) I get a busfault error. In this case I can identify (using watchpoints) that the USB app is again using memory that overlaps with my data array. When transmission begins the mcu hangs and it indicates a busfault.
How should I try to debug this behavior and how can I find the process that is violating my data? Is there a way to specify the address where I initialize my data arrays to maybe avoid the overlap?
Regards,
Frik
It seems, however, that somehow the USB is writing to a certain memory address which is also contained in one of my data arrays, and I loose that particular data.
The problem occurs at the same address every time (word at 0x20000CD0). Using the debugger I could assert that the data is sampled correctly, but when the code proceeds to USB tasks the particular memory is overwritten before being transmitted to the host.
I cannot identify the precise command that is responsible for the write operation, but I am convinced that is the usb - watchpoint does not pick it up???
The above happens with the USBD_VCOM app on the XMC4400.
When I try to use the old app (USBVC001) I get a busfault error. In this case I can identify (using watchpoints) that the USB app is again using memory that overlaps with my data array. When transmission begins the mcu hangs and it indicates a busfault.
How should I try to debug this behavior and how can I find the process that is violating my data? Is there a way to specify the address where I initialize my data arrays to maybe avoid the overlap?
Regards,
Frik
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Unexpected DMA behavior
I am trying to use the DMA to transfer multi-blocks of data from memory to the TBUF of a USIC. The DMA is set to Hardware handshake for the destination.
The behavior at the moment is totally unpredictable. Sometimes it works correctly and sometimes only 0xFFFF is transferred.
There are 2 things that seem strange to me:
1. The DMA transfer starts immediately when it is enabled. As the transmit buffer interrupt from the USIC is a pulse I would expect to have to trigger the interrupt by software to start the DMA transfer. Is the behavior normal or have I set the USIC interrupt incorrectly?
2. The Overrun bit in the DLR is getting set. According to the documentation this only happens when the next Service Request comes before the DMA acknowledges the previous request. I cannot believe the DMA is taking longer to acknowledge the interrupt than the USIC needs to transmit 16bits of data. What could be the problem here? Does the overrun status have an effect on the next service request?
I cannot find any reason why the DMA is not working reliably. The above points are only a guess of what may be going wrong.
Does anyone have an example of DMA transfers from memory to peripheral using link lists?
The behavior at the moment is totally unpredictable. Sometimes it works correctly and sometimes only 0xFFFF is transferred.
There are 2 things that seem strange to me:
1. The DMA transfer starts immediately when it is enabled. As the transmit buffer interrupt from the USIC is a pulse I would expect to have to trigger the interrupt by software to start the DMA transfer. Is the behavior normal or have I set the USIC interrupt incorrectly?
2. The Overrun bit in the DLR is getting set. According to the documentation this only happens when the next Service Request comes before the DMA acknowledges the previous request. I cannot believe the DMA is taking longer to acknowledge the interrupt than the USIC needs to transmit 16bits of data. What could be the problem here? Does the overrun status have an effect on the next service request?
I cannot find any reason why the DMA is not working reliably. The above points are only a guess of what may be going wrong.
Does anyone have an example of DMA transfers from memory to peripheral using link lists?
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DMA Register Mapping
Hi all,
I have a question regarding the mapping of DMA registers with SW structures. One can find the following structure data type in `xmc_dma.h`.
Attachment 2266
However, the reference manual shows the layout a bit differently, as seen below.
Attachment 2267
It is relatively straightforward that the members of the structure are arrays that represent collections of registers (i.e. RAWTFR, RAWBLOCK, RAWSRCTRAN... are collected under RAWCHEV[10]). Also, I have no question regarding the size of arrays - for instance, RAW* array is 32 bits long and there is 8 bits of space between 02E0 and 02E8, where STATUS* starts.
What I don't understand is why STATUSCHEV, which is seemingly supposed to contain STATUS* register values (that are obtained by passing RAW* values and MASK* values through a bit-wise AND gate, if I were to speculate), contains the values that belong in STATUSINT? To explain, a workspace search (CTRL+ALT+G) for STATUSCHEV invocation returns the following results,
Attachment 2268
There are 4 other invocations that access array members [2], [4] and so forth, until [8]. These accesses fetch the combined status, which - what it seems like - is supposed to be done by accessing STATUSINT. On the other hand, STATUSINT is not invoked at all (again, as per workspace search).
Now, the question is - which register is which. And as a follow-up - is there any file that is generated by the compiler that would show the mapping of such structures to peripheral registers? (I am thinking along the lines of .map files that show the mapping of variables in memory, etc.)
Edit: While we are on the topic of DMAs, I was wondering if the programmable registers are the ones that GPDMA actually uses, or are there shadow registers that programmable registers are copied into?
Thank you in advance and best regards,
Andrey
I have a question regarding the mapping of DMA registers with SW structures. One can find the following structure data type in `xmc_dma.h`.
Attachment 2266
However, the reference manual shows the layout a bit differently, as seen below.
Attachment 2267
It is relatively straightforward that the members of the structure are arrays that represent collections of registers (i.e. RAWTFR, RAWBLOCK, RAWSRCTRAN... are collected under RAWCHEV[10]). Also, I have no question regarding the size of arrays - for instance, RAW* array is 32 bits long and there is 8 bits of space between 02E0 and 02E8, where STATUS* starts.
What I don't understand is why STATUSCHEV, which is seemingly supposed to contain STATUS* register values (that are obtained by passing RAW* values and MASK* values through a bit-wise AND gate, if I were to speculate), contains the values that belong in STATUSINT? To explain, a workspace search (CTRL+ALT+G) for STATUSCHEV invocation returns the following results,
Attachment 2268
There are 4 other invocations that access array members [2], [4] and so forth, until [8]. These accesses fetch the combined status, which - what it seems like - is supposed to be done by accessing STATUSINT. On the other hand, STATUSINT is not invoked at all (again, as per workspace search).
Now, the question is - which register is which. And as a follow-up - is there any file that is generated by the compiler that would show the mapping of such structures to peripheral registers? (I am thinking along the lines of .map files that show the mapping of variables in memory, etc.)
Edit: While we are on the topic of DMAs, I was wondering if the programmable registers are the ones that GPDMA actually uses, or are there shadow registers that programmable registers are copied into?
Thank you in advance and best regards,
Andrey
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XMC Trainings on Lighting Application, Microcontroller basics
XMC trainings are available on the XMC4000 and XMC1000 product websites.
The training materials can be downloaded from the respective XMC product pages, under Documents >> Training:
XMC4000XMC1000
- Introduction to Microcontroller World - new
- Application - Lighting - XMC in LED Lighting Applications - updated
The training materials can be downloaded from the respective XMC product pages, under Documents >> Training:
XMC4000XMC1000
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About Boot loader
Hi Min Wei,
As per above mentioned process for boot loader, after power on reset i want to read the file from SD card and want to store it in Flash either by overwriting old firmware or by making a new location for
new firmware.My primary concern should be not to disturb the old firmware, if any problem occurs in the update process.Please guide me for this implementation.
Thanks,
M. Ramarao.
As per above mentioned process for boot loader, after power on reset i want to read the file from SD card and want to store it in Flash either by overwriting old firmware or by making a new location for
new firmware.My primary concern should be not to disturb the old firmware, if any problem occurs in the update process.Please guide me for this implementation.
Thanks,
M. Ramarao.
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ABM Header
I am looking forward to this example. I am also interested in how to set up the linker script for two co-existing firmwares? And if one failts, the second will be used for boot?
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ETH_LWIP_0 and DP83848C
Ok, nevermind. Stupid me didn't change the PHY-address. Setting the address to 1 made the board ping-able with the DP83848-setting.
Regards,
Niclas
Regards,
Niclas
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Use UART over USB at XMC1100 BootKit
Yes, Virtual COM Port is there in HW-Manager...
But it don't goes over DEBUG XMC4500 to XMC1100 ...
I think, that virtual COM Port is only for use with X-Spy ???
May, there is a way to use it with own Terminal-SW? That's the question ...
But it don't goes over DEBUG XMC4500 to XMC1100 ...
I think, that virtual COM Port is only for use with X-Spy ???
May, there is a way to use it with own Terminal-SW? That's the question ...
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New XMC4300/ XMC4800 Relax EtherCAT® Evaluation Kit
Microcontroller series XMC4800 for ease-of-use EtherCAT® implementation
The XMC4800 offers the EtherCAT® community a new previously unimaginable benchmark for ease of implementation.
It is the markets first-ever microcontroller to integrate an EtherCAT® node on an ARM® Cortex®-M controller with on-chip flash and analog/mixed signal capabilities.
The XMC4800 enables the most compact designs, eliminating the need for a dedicated EtherCAT® ASIC, external memory and crystal. Designers benefit from BOM cost and PCB space savings.
Attachment 2278
New microcontroller series XMC4300 simplifying EtherCAT® implementation
The new XMC4300 microcontroller series further reduces complexity in EtherCAT® implementation and cost in factory automation, industrial motor control, I/O modules and robotics.
The XMC4300 series was specifically developed for EtherCAT® industrial applications, where cost pressure places a premium on design flexibility, connectivity and performance without compromise to EtherCAT® communication features.
Attachment 2279
Product Brief XMC4300 4800 Series:
http://bit.ly/XMC4300_XMC4800_ProductBrief
XMC4800 Relax EtherCAT kit featured on RS-Components:
http://bit.ly/XMC4800_relax_ethercat_kit_RS
For more information:
http://bit.ly/XMC4300_XMC4800_EtherCAT
The XMC4800 offers the EtherCAT® community a new previously unimaginable benchmark for ease of implementation.
It is the markets first-ever microcontroller to integrate an EtherCAT® node on an ARM® Cortex®-M controller with on-chip flash and analog/mixed signal capabilities.
The XMC4800 enables the most compact designs, eliminating the need for a dedicated EtherCAT® ASIC, external memory and crystal. Designers benefit from BOM cost and PCB space savings.
Attachment 2278
New microcontroller series XMC4300 simplifying EtherCAT® implementation
The new XMC4300 microcontroller series further reduces complexity in EtherCAT® implementation and cost in factory automation, industrial motor control, I/O modules and robotics.
The XMC4300 series was specifically developed for EtherCAT® industrial applications, where cost pressure places a premium on design flexibility, connectivity and performance without compromise to EtherCAT® communication features.
Attachment 2279
Product Brief XMC4300 4800 Series:
http://bit.ly/XMC4300_XMC4800_ProductBrief
XMC4800 Relax EtherCAT kit featured on RS-Components:
http://bit.ly/XMC4800_relax_ethercat_kit_RS
For more information:
http://bit.ly/XMC4300_XMC4800_EtherCAT
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lwip hangs in "release" build
Hi,
I tested your software in release mode with Optimization level set to None and everything is working good now.
Attachment 2281
I tested your software in release mode with Optimization level set to None and everything is working good now.
Attachment 2281
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How to Migrate from XMC4500 to XMC4700
Quote:
Originally Posted by Pitcher
![View Post]()
Hello community, here my first question:
Is it possible, to migrate a project for the XMC4500 to the XMC4700?
As the XMC4700 includes also the features of the XMC4500, it should be possible to keep the already installed apps.
I found the migrate option in DAVE, but it offers only the derivates of the XMC4500.
Reason: we started with the RelaxKit (with 4500) for the first steps but our design will have the 4700.
Thanks and regards
Is it possible, to migrate a project for the XMC4500 to the XMC4700?
As the XMC4700 includes also the features of the XMC4500, it should be possible to keep the already installed apps.
I found the migrate option in DAVE, but it offers only the derivates of the XMC4500.
Reason: we started with the RelaxKit (with 4500) for the first steps but our design will have the 4700.
Thanks and regards
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