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EBU settings with Dave4

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Hi oreste,

we have the same problem for XMC4800 and it would be very nice if you could implement such an EBU CONFIG APP in the next time.

In the meantime, do you have an example how to initialize the EBU without an APP?

Introduced year of TC23X

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hi

for a documentation purpose i need to know Introduced date of Infineon TC23X ?

Regards
Rajeetharan.

float and int value TX problem in UART(XMC4500, DAVE4)

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HI~

I started DAVE4 and XMC4500 to use UART TX and RX
and I checked the format of UART TX , RX function such as
-UART_STATUS_t UART_Transmit(const UART_t *const handle, uint8_t* data_ptr, uint32_t count)
-UART_STATUS_t UART_Receive(const UART_t *const handle, uint8_t* data_ptr, uint32_t count)

I would like to Transmit float and int value(ex: float a=2.3453, int b=23) by UART TX
How do I solve this probl

UART SAMPLE)

#include <DAVE.h> //Declarations from DAVE Code Generation (includes SFR declaration)

int main(void)
{


float a=2.3453, int b=23; //How do I Transmit float and int variable in UART of DAVE4 ??

uint8_t init_data[] = "Press enter if you want to receive a message";
uint8_t send_data[] = "\nHello world!";
uint8_t read_data = 0x0;

DAVE_Init(); /* Initialization of DAVE APPs */

/* Transmit the introduction message */
UART_Transmit(&UART_0, init_data, sizeof(init_data));

while(1U)
{
/* Read the data */
UART_Receive(&UART_0, &read_data,1);
if(read_data == 0xD)
{
/* Transmit the message */
UART_Transmit(&UART_0, send_data, sizeof(send_data));
read_data = 0x0;
}
}
return 0;
}

Bootloader running from Flash

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Yes, you can. Just do it.

Quote:

Originally Posted by Jorge66 View Post
Hello all,

Question is :
Cannot we reprogram a simple Flash sector (with the final app hex) while running loader
from another sector in Flash ?
Is it conceivable to jump to another flash sector to reprogram previous one ?
Or is it this approach a dead end ?

Thanks for your advise

Jorge

Raw Ethernet issues with XMC4800 on Relax EtherCAT card

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Hi,

We are communicating between a PC and the XMC4800 Relax EtherCAT board via Ethernet. The communication works well until we have sent ~1MB. At that point memory becomes corrupted.
We are using raw ethernet non-jumbo frames, sending and receving packages with payload of 1496 bytes.
We are using the file xmc_eth_phy_ksz8081ml.c (2015-06-20) for the phy device.

Everything works well until we have sent ~1MB. At that point, the buffer send_frame[] starts getting corrupted from its lower bytes and up. It's as if there is a buffer overflow in the memory before that location. In the memory map, the buffer recv_frame[] is located before send_frame. This made me suspicious that the recv_frame overwrites its boundaries, but after investigating that is not the case. Moving send_frame[] to another address in ram (by adding another dummy-array between recv_frame and send_frame) will make the memory corruption happen later (around 2MBs).

Running the application in DEBUG mode works well. This issue is not happening in DEBUG.

Below is the code for handling the Ethernet communication. We are sending and receving approximately 100kB/s in bursts.

Any ideas of what could cause this?

Thanks
Rickard

Code:

/*
 * Ethernet.c
 */

#include "Ethernet.h"
#include "EventLoop.h"
#include <xmc_gpio.h>
#include <xmc_eth_mac.h>
#include <xmc_eth_phy.h>

#define RX_BUFSIZE                53300
#define TX_BUFSIZE                5000
uint8_t rxBufEth[2][RX_BUFSIZE] = {{0},{0}};
uint8_t txBufEth[TX_BUFSIZE] = {0};
uint32_t receivedBytes[2] = {0};
uint32_t bytesToSend = 0;

static uint32_t readIndex = 0;
static uint32_t writeIndex = 0;

#define ETH_PHY_ADDR 0

#define ETH_RXD1    P2_3
#define ETH_RXD0    P2_2
#define ETH_RXER    P2_4
#define ETH_CLK_RMII P15_8
#define ETH_TX_EN    P2_5
#define ETH_TXD1    P2_9
#define ETH_TXD0    P2_8
#define ETH_CRS_DV  P15_9
#define ETH_MDIO    P2_0
#define ETH_MDC      P2_7

/* MAC ADDRESS*/
#define MAC_ADDR0  0x00
#define MAC_ADDR1  0x00
#define MAC_ADDR2  0x45
#define MAC_ADDR3  0x19
#define MAC_ADDR4  0x03
#define MAC_ADDR5  0x00
#define MAC_ADDR    ((uint64_t)MAC_ADDR0 | \
                ((uint64_t)MAC_ADDR1 << 8) | \
                ((uint64_t)MAC_ADDR2 << 16) | \
                ((uint64_t)MAC_ADDR3 << 24) | \
                ((uint64_t)MAC_ADDR4 << 32) | \
                ((uint64_t)MAC_ADDR5 << 40))

#define XMC_ETH_MAC_NUM_RX_BUF (4)
#define XMC_ETH_MAC_NUM_TX_BUF (4)

#define USERDATA 14

static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t rx_desc[XMC_ETH_MAC_NUM_RX_BUF] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t tx_desc[XMC_ETH_MAC_NUM_TX_BUF] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) uint8_t rx_buf[XMC_ETH_MAC_NUM_RX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) uint8_t tx_buf[XMC_ETH_MAC_NUM_TX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));

static XMC_ETH_PHY_CONFIG_t eth_phy_config =
{
                .interface = XMC_ETH_LINK_INTERFACE_RMII,
                .enable_auto_negotiate = true
};

static XMC_ETH_MAC_t eth_mac =
{
                .regs = ETH0,
                .address = MAC_ADDR,
                .rx_desc = rx_desc,
                .tx_desc = tx_desc,
                .rx_buf = &rx_buf[0][0],
                .tx_buf = &tx_buf[0][0],
                .num_rx_buf = XMC_ETH_MAC_NUM_RX_BUF,
                .num_tx_buf = XMC_ETH_MAC_NUM_TX_BUF
};

static __attribute__((aligned(4))) uint8_t recv_frame[XMC_ETH_MAC_BUF_SIZE];
static __attribute__((aligned(4))) uint8_t send_frame[XMC_ETH_MAC_BUF_SIZE];

unsigned char xmc_mac[6] =  {0x00, 0x00, 0x45, 0x19, 0x03, 0x00};
unsigned char pc_mac[6] =  {0x54, 0xEE, 0x75, 0x56, 0xA8, 0x09};
unsigned char ethType[2] =  { 0xb5, 0x88 };

void ETH_MAC_Init(void);

void Ethernet_Initialize()
{
        ETH_MAC_Init();

        memset(send_frame, 0, XMC_ETH_MAC_BUF_SIZE);
        memcpy(&send_frame[0], &pc_mac[0], 6);                // destination
        memcpy(&send_frame[6], &xmc_mac[0], 6);        // source
        memcpy(&send_frame[12], &ethType[0], 2);        // ethType
}

int32_t CheckCorruption()
{
        int32_t res = memcmp(&send_frame[0], &pc_mac[0], 6);
        res |= memcmp(&send_frame[6], &xmc_mac[0], 6);
        res |= memcmp(&send_frame[12], &ethType[0], 2);
        return res;
}

void Ethernet_StartTransmit(uint8_t* data, uint32_t count)
{
        memcpy(&send_frame[16], &data[0], count);

        if (CheckCorruption())
        {
                XMC_GPIO_ToggleOutput(XMC_GPIO_PORT3, 0U);
        }

        XMC_ETH_MAC_SendFrame(&eth_mac, &send_frame[0], count + 16, 0);
}

uint32_t Ethernet_GetBuffer(uint8_t** buf)
{
        uint32_t ret = receivedBytes[readIndex];
        receivedBytes[readIndex] = 0;
        *buf = &rxBufEth[readIndex][0];
        readIndex = readIndex == 0 ? 1 : 0;
        return ret;
}

// ethernet initialisation
// from a tip by Jesus @ Infineon forum
void ETH_MAC_Init(void)
{
        XMC_ETH_MAC_PORT_CTRL_t port_control;
        XMC_GPIO_CONFIG_t gpio_config;

        gpio_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
        XMC_GPIO_Init(ETH_RXD0, &gpio_config);
        XMC_GPIO_Init(ETH_RXD1, &gpio_config);
        XMC_GPIO_Init(ETH_CLK_RMII, &gpio_config);
        XMC_GPIO_Init(ETH_CRS_DV, &gpio_config);
        XMC_GPIO_Init(ETH_RXER, &gpio_config);
        XMC_GPIO_Init(ETH_MDIO, &gpio_config);

        port_control.mode = XMC_ETH_MAC_PORT_CTRL_MODE_RMII;
        port_control.rxd0 = XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2;
        port_control.rxd1 = XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3;
        port_control.clk_rmii = XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8;
        port_control.crs_dv = XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9;
        port_control.rxer = XMC_ETH_MAC_PORT_CTRL_RXER_P2_4;
        port_control.mdio = XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0;
        XMC_ETH_MAC_SetPortControl(&eth_mac, port_control);

        XMC_ETH_MAC_Init(&eth_mac);

        XMC_ETH_MAC_DisableJumboFrame(&eth_mac);

        gpio_config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
        gpio_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
        gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_8_AF_ETH0_TXD0);
        XMC_GPIO_Init(ETH_TXD0, &gpio_config);

        gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_9_AF_ETH0_TXD1);
        XMC_GPIO_Init(ETH_TXD1, &gpio_config);

        gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_5_AF_ETH0_TX_EN);
        XMC_GPIO_Init(ETH_TX_EN, &gpio_config);

        gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_7_AF_ETH0_MDC);
        XMC_GPIO_Init(ETH_MDC, &gpio_config);

        XMC_GPIO_SetHardwareControl(ETH_MDIO, P2_0_HWCTRL_ETH0_MDO);

        XMC_ETH_PHY_Init(&eth_mac, ETH_PHY_ADDR, &eth_phy_config);

        while(XMC_ETH_PHY_GetLinkStatus(&eth_mac, ETH_PHY_ADDR) != XMC_ETH_LINK_STATUS_UP);

        XMC_ETH_LINK_SPEED_t speed = XMC_ETH_PHY_GetLinkSpeed(&eth_mac, ETH_PHY_ADDR);
        XMC_ETH_LINK_DUPLEX_t duplex = XMC_ETH_PHY_GetLinkDuplex(&eth_mac, ETH_PHY_ADDR);

        XMC_ETH_MAC_SetLink(&eth_mac, speed, duplex);

        // Enable ethernet interrupts
        XMC_ETH_MAC_EnableEvent(&eth_mac, XMC_ETH_MAC_EVENT_RECEIVE);

        NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 0));
        NVIC_ClearPendingIRQ(ETH0_0_IRQn);
        NVIC_EnableIRQ(ETH0_0_IRQn);

        XMC_ETH_MAC_EnableTx(&eth_mac);
        XMC_ETH_MAC_EnableRx(&eth_mac);
}

// Ethernet receive interrupt routine
void ETH0_0_IRQHandler(void)
{
        uint32_t status;
        uint32_t len;

        status = XMC_ETH_MAC_GetEventStatus(&eth_mac);

        if (status & XMC_ETH_MAC_EVENT_RECEIVE)
        {
                XMC_ETH_MAC_ClearEventStatus(&eth_mac, XMC_ETH_MAC_EVENT_RECEIVE);

                len = XMC_ETH_MAC_GetRxFrameSize(&eth_mac);
                XMC_ETH_MAC_ReadFrame(&eth_mac, &recv_frame[0], len);

                if (memcmp(&recv_frame[0], &xmc_mac, 6))
                { // packet for us?
                        return;                                    // nope
                }

                uint16_t fragmentationOffset = recv_frame[14] | ((recv_frame[15] & 0x7F) << 8);
                uint16_t offset = 8 * fragmentationOffset;
                uint32_t dataLength = len - 14 - 2;

                if (receivedBytes[writeIndex] + dataLength > RX_BUFSIZE)
                {
                        return;
                }

                memcpy(&rxBufEth[writeIndex][offset], &recv_frame[16], dataLength);
                receivedBytes[writeIndex] += dataLength;

                if (ethData->moreFragments)
                {
                        // Wait for more data
                        return;
                }

                writeIndex = writeIndex == 0 ? 1 : 0;

                EventLoop_events |= ReceivedEthernetPackageEventFlag;
        }
}

SEGGER_RTT XMC4500 Relax Kit

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Thank you, now its working perfect.

Andi

XMC1400 external VAREF for ADC issue

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Hello,

i would like to use the external VAREF (VDD Pin = 5V) for reading ADC results from 5V Sensors

and (VDDP= 3,3V) for digital IO (communication with other ics and so on...

1st question: is that in principle possible? --> VDD > VDDP ?
2nd question how can i activate the external VAREF? --> I am using DAVE 4.3.2 and the ADC Measurement App 4.1.22 --> the generated code looks:

Code:

/*********************** C3 Configurations ************************************/


/*C3 ADC Channel configuration structure*/
XMC_VADC_CHANNEL_CONFIG_t  C3_ch_config =
{
  .input_class                = (uint32_t) XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS0,  /* Global ICLASS 0 selected */
  .lower_boundary_select          = (uint32_t) XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0,
  .upper_boundary_select          = (uint32_t) XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0,
  .event_gen_criteria        = (uint32_t) XMC_VADC_CHANNEL_EVGEN_NEVER, /*Channel Event disabled */
  .sync_conversion                    = (uint32_t) 0,                            /* Sync feature disabled*/
  .alternate_reference        = (uint32_t) XMC_VADC_CHANNEL_REF_INTREF,  /* Internal reference selected */  //----------------------------------------------this line to external ref ?!
  .result_reg_number          = (uint32_t) 13,                          /* GxRES[13] selected */
  .use_global_result          = (uint32_t) 0,                                              /* Use Group result register*/
  .result_alignment          = (uint32_t) XMC_VADC_RESULT_ALIGN_RIGHT,  /* Result alignment - Right Aligned*/
  .broken_wire_detect_channel = (uint32_t) XMC_VADC_CHANNEL_BWDCH_VAGND, /* No Broken wire mode select*/
  .broken_wire_detect                  = (uint32_t) 0,                                    /* No Broken wire detection*/
  .bfl                        = (uint32_t) 0,                            /* No Boundary flag */
  .channel_priority          = (uint32_t) 0,                                    /* Lowest Priority 0 selected*/
  .alias_channel              = (int8_t) -1,                        /* ALIAS is Disabled*/
};

/*C3 Result configuration structure*/
XMC_VADC_RESULT_CONFIG_t C3_res_config =
{
  .data_reduction_control  = (uint8_t) 0,  /* No Accumulation */
  .post_processing_mode    = (uint32_t) XMC_VADC_DMM_REDUCTION_MODE,
  .wait_for_read_mode            = (uint32_t) 0,  /* Disabled */
  .part_of_fifo                  = (uint32_t) 0 , /* No FIFO */
  .event_gen_enable              = (uint32_t) 0  /* Disable Result event */
};

/* C3 ADC channel Handle */
ADC_MEASUREMENT_CHANNEL_t ADC_MEASUREMENT_C3_handle =
{
  .ch_num        = (uint8_t) 2,
  .group_handle  = (VADC_G_TypeDef*)(void*) VADC_G1,
  .group_index        = (uint8_t) 1,
  .ch_handle        = (XMC_VADC_CHANNEL_CONFIG_t*) &C3_ch_config,
  .res_handle        = (XMC_VADC_RESULT_CONFIG_t*) &C3_res_config,
};

Attachment 2691
Attachment 2692

According to these pictures i thought its working without any problems.

But in my test setup goes something wrong: when i conect VDD to 5V then the VDDP Pins (normally 3,3V) rise up to 4V. When i disconect VDD, then is the reference voltage 2,5V at this pin.

Can anybody explain me what i am doing wrong?

Big Thnaks!

Andi
Attached Images

XMC4800 + (Rasperry Pi) + cycloneTCP tcp/ip stack

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To investigate my problem further, I have made a Dave application with the HTTP_SERVER and LWIP apps. This works fine out of the box.: I can browse to the default webpage.

However, when I add the CMSIS_RTOS, I cannot browse anymore to the default webpage. I suspect I have nothing to do in my main() function except for starting the kernel with osKernelStart(); ?
Even a simple ping doesn't work anymore.
During debugging, the tcpip_thread(void *arg) method is executed and the messages for TCP_CONNECT and TCP_BIND are processed. Then, it seems no connections are accepted anymore.

Is there someone who can help me? What am I doing wrong ?

Thanks.

http://goldenhealthcenters.com/skin-balance-cream/

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Skin Balance Cream Product Reviews- It is not therefore unusual nonetheless usually forgotten solution assessments performed inside the internet today. Everybody simply dismissed how it may influence them as Skin Care Tips a consumer and what's that evaluation about. Customers must be conscious enough in performing some particular study into some things like when they desire to discover that greatest vision gel in the market. You can not blame everyone down the road if you experienced some pitfalls since you are too dash in getting that kind of solution.

Chlorine is not nontoxic and also the destruction it can to your skin and also to your current health from inhalation is not any laughing matter. And you surely don't need to age any earlier than you need to. That means there is more than one explanation to consider a shower filter's installation.

http://goldenhealthcenters.com/skin-balance-cream/

"Failed to halt processor" on Memtool

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Using Memtool, after enabling the global R/W protection on my XMC4500 (1 MB), I get the message "Failed to halt processor" when I try to connect.

It looks like the miniWiggler does connect with the Cortex-M core, but the Flash operations are not available since the processor is still running.

Any ideas of how to disable the global protection? Any ideas of how to make the processor halt?

Thanks

Problems with In-Application-Programming of Data-Flash with extended Code Memory

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Hello,

I need to store and erase parameter data via In-Application-Programming in the XC886 32kB Flash Device.

Moreover I have a lack of code memory. So I use 7kB of the Data-Flash as additional code memory.
This works fine. So the Code is executed well, independent if it is stored in the Program-Flash-Banks (0x0000…0x5FFF)
or in D-Flash-Bank 1 or in D-Flash-Bank 0.

Attachment 2695

If only D-Flash-Bank 1 is written with Code-Memory (till 0x6FFF), everything works fine. I can erase and write to the flash
without problems.

The point is: If D-Flash-Bank 0 is written with Code-Memory, the In-Application-Programing-functions don’t work anymore.
Sometimes I can’t erase the parameters (the function stays in an endless loop) and writing to the flash works.
Sometimes I can’t write to the flash and erasing works.

(Note: I am sure that the code memory is not in the sectors which I use as data and I am sure that I do not erase
or overwrite code memory)

I have attached a file with the Flash-functions I use. I relocated these functions via linker instructions to different places
in the code memory (0x7800, 0x6800, 0x5800, 0x2800, 0x2200). On some of these places the
In-Application-Programing-functions work again, but if I add or remove e.g. 100 Bytes of code, I have the same error.

Has anybody an idea?

BGT24-RFB2412 Board - Transparent connector

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Dear dheerajkc and buison1412

I face the problem as you mentioned above and I have consulted the engineer in Infineon. He said that the software for FMCW will be upgraded in the near future.

Now I have got the data via USB-audio-device using the software provided by Infineon. But I don't know how to pre-process the data because I have no idea about how to distinguish the IFI and IFQ infromation
Could you help me?
zhangzhenyuangm@gmail.com
Thank you for your reply

LIN Status Flags on TLE9877QXA40

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Hello!

First of all, sorry if I post in the wrong place, I didn't find an specific place for TLE Microcontrollers. I am facing a Problem, and maybe you could help me.

I try to use LIN Communication, but it doesn't work correctly. I configured everything and I get to Interrupt when I receive Information via LIN. For understanding the different steps of the data I receive, I have to work with Flags (EOFSYN and BRK), but These Flags are never set. When I read them, they are always 0.

SYNEN Bit is also enabled. Where could be the Problem? If it is more complicated than a possible easy mistake, and you need the code I wrote, I will kindly update with it!.


UPDATE: The Problem is solved. The cause was a bad configuration of BGSEL for Synch detection!. But I have a question. When Flags SYNCH and BRK are set, it means that the next Byte is the id, but when I read it at SBUF Returns me 0. What could it be?

Thank you.
Kind Regards.

Mjag

Create a TC275 project with iLLD in tasking

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I want to create a TC275 project with iLLD in tasking , but I do not know what to do , I did not find the relevant information about this .
How did you do that? Can someone help me ?

ASC BSL timeout with XMC1400

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Hi,

I want to use the XMC1400 with ASC BSL timeout option. According to the datasheet i should be able to configure the timeout with x*0.333s where x is the BSLTO of the BMI register.

By trial and error i found out that in reality i get the following timeout: 1.5s + x*0.5ms (i tried all possible values of BSLTO and measured the boot time). Can someone confirm this? Is this a silicon bug or an error in the datasheet?

For our application we need the 333ms option, a minimum boot time of 2 seconds is too large.

Thanks!

How to setting ASCBootloader in XMC4500 Relax kit

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Hello

I'm trying to use ASCBootloader in XMC4500 Relax kit

but I don't succeed

I already read XMC4000 - ASC Bootstrap Loader pdf

I'm wondering

First, I can use ASCLoader in XMC4500 Relax kit?(not hex board)

Second, Relax kit doesn't have DIP switch, then how to setting TMS and TCK pin in XMC4500 Relax kit?

Finally, I want to know if there is related code(I want XMC4500 Relax kit, not hex board)

Please help me

thanks

Architecture Difference TC1.3 and TC1.6

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Hello,

What is the Difference between TC1.6 CPU architecture and TC1.3
Thanks,
Ajeesh A.

Absolute Maximum ratings of RF Devices

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Hi,

Can someone offer some insight please relating to absolute maximum ratings of RF devices? I outline an RF FET case study below:

Absolute maximum rating from datasheet
Vgsmax=-10 to +3V

Relevant Device RF Data @ operational Frequency
Zin=+17.8-j16.

Relevant Operational Details
RF power in=29dBm (794mW)
Quiescent Gate Voltage=-1V (DC bias)

Calculations
I did a fundamental “Ohm’s law” type calculation to determine what the RF voltage swing would be on the device input (Gate)
Vpp=2*sqrt(2*P*Zin), Vpp=12.3V so that the RF swing is between -7.2 and +5.2V. The analysis suggests that at the top of the RF swing, the device Vgsmax is exceeded, and this can therefore be seen as a potential failure scenario.
I have posed this question to colleagues, some of whom claim that the “Absolute Max rating” described is purely a DC parameter, and that that it did not apply to RF. Same colleagues however, could never provide theoretical validation of this assertion.
Can someone please validate the logic here or otherwise explain why the thinking is flawed and offer an alternative idea to relate absolute DC limits and operational RF extremes.

Thanks,
BK Parker

Multican_config app

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Where is expected bug-fix for ID=0?

XMC4200 PSRAM Mapping

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We're using the XMC4200 and look to be running into size constraints with the memory. Looking at Memory Settings page in DAVE it shows:

Name Type Start Address End Address Size
PSRAM1 RAM 0x1FFFE000 0x1FFFFFFF 0x2000
DSRAM1 RAM 0x20000000 0x20005FFF 0x6000

So PSRAM1 is 8KB and DSRAM1 is 24KB. We're supposed to have 40KB total and expecting 16KB on PSRAM1 but total is only 32KB.

Can we change the PSRAM1 size to 16KB and if so, what is the addressing we should use?

We notice the DSRAM1 addressing is consecutive with the PSRAM1 addressing so assume we need to change addressing for both.

Thanks
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