hello
can you please let me know the state of the flash controller, after reset? asleep or awake?
if asleep, would the following seem feasible
/* read 2 blocks from nvm to sram */
XMC_FLASH_ExitSleepMode();
while(XMC_FLASH_IsBusy());
XMC_FLASH_ClearStatus();
XMC_FLASH_ReadBlocks(XMC1100_SECTOR15_PAGE01_ADDR, (uint32_t *) &buffer, 2);
while(XMC_FLASH_IsBusy());
XMC_FLASH_EnterSleepMode();
also
just a general question about design of a pcb with the XMC1100
after reviewing the XMC1100 layout (tssop16), there is no boot pin like other comparable cortex m0 chips
i am slowly reading the Reference Manual V1.2 2014-11, have not carefully read Bootstrap Loaders (BSL) and User Routines yet
is RxD at P0.14 and TxD at P0.15, all the pins that are required to program the XMC1100?
regards
enzo
can you please let me know the state of the flash controller, after reset? asleep or awake?
if asleep, would the following seem feasible
/* read 2 blocks from nvm to sram */
XMC_FLASH_ExitSleepMode();
while(XMC_FLASH_IsBusy());
XMC_FLASH_ClearStatus();
XMC_FLASH_ReadBlocks(XMC1100_SECTOR15_PAGE01_ADDR, (uint32_t *) &buffer, 2);
while(XMC_FLASH_IsBusy());
XMC_FLASH_EnterSleepMode();
also
just a general question about design of a pcb with the XMC1100
after reviewing the XMC1100 layout (tssop16), there is no boot pin like other comparable cortex m0 chips
i am slowly reading the Reference Manual V1.2 2014-11, have not carefully read Bootstrap Loaders (BSL) and User Routines yet
is RxD at P0.14 and TxD at P0.15, all the pins that are required to program the XMC1100?
regards
enzo