I am using a tricore TC277 with Hightec compilers alsong with infineon illds.
I was trying to configure TIM0 , Channel0 for PWM measurement from a port pin.
When i try to configure the clock(GTM CMU global clock used for TIM module) using the following snippet of code I am getting a trap 4 triggered while these execute
(Bus/Peripheral Trap - Temporal asynchronous error). I am not able to understand why this error occurs as I am following Infineon's sample code where they have done exactly the same.
I checked the documentation and nothing much is mentioned about the TRAP in that as well.
/* configure CMU */
GTM_CMU_GCLK_NUM.U = 0x0000FFFF;
GTM_CMU_GCLK_DEN.U = 0x0000FFFF; <==== Trap(4) triggered here
GTM_CMU_CLK_0_CTRL.U = 0x00000000 | div; /* factor 5 division (20MHz) */
GTM_CMU_CLK_EN.U = 0x00008002; /* clock 0 and 7 enable */
Did anyone face such an issue with TIM0CH0 CMU_CLK configuration and got similar issues or used another method to configure which I would be glad to know about.
Thanks in advance.
I was trying to configure TIM0 , Channel0 for PWM measurement from a port pin.
When i try to configure the clock(GTM CMU global clock used for TIM module) using the following snippet of code I am getting a trap 4 triggered while these execute
(Bus/Peripheral Trap - Temporal asynchronous error). I am not able to understand why this error occurs as I am following Infineon's sample code where they have done exactly the same.
I checked the documentation and nothing much is mentioned about the TRAP in that as well.
/* configure CMU */
GTM_CMU_GCLK_NUM.U = 0x0000FFFF;
GTM_CMU_GCLK_DEN.U = 0x0000FFFF; <==== Trap(4) triggered here
GTM_CMU_CLK_0_CTRL.U = 0x00000000 | div; /* factor 5 division (20MHz) */
GTM_CMU_CLK_EN.U = 0x00008002; /* clock 0 and 7 enable */
Did anyone face such an issue with TIM0CH0 CMU_CLK configuration and got similar issues or used another method to configure which I would be glad to know about.
Thanks in advance.