Hello,
i do not know if this will help but it is written in page 14 in the datasheet the following remark:
Important: Since the UV and MV (as well as the TE and W4S) bits used for generating the ERR signal are preset
to High during UVLO, the ERR pin is Low after power up. Therefore the ERR signal requires to be explicitly cleared
after power up. At least one read access to the GLERR and INTERR registers is needed to update those status
bits and thus release the ERR pin.
I hope this would help you
Bests
i do not know if this will help but it is written in page 14 in the datasheet the following remark:
Important: Since the UV and MV (as well as the TE and W4S) bits used for generating the ERR signal are preset
to High during UVLO, the ERR pin is Low after power up. Therefore the ERR signal requires to be explicitly cleared
after power up. At least one read access to the GLERR and INTERR registers is needed to update those status
bits and thus release the ERR pin.
I hope this would help you
Bests