By using gateway with FIFO, normally one message object is configured as RxMO on gateway source side, and a couple of message objects are configured as TxFIFO MOs on gateway destination side.
the 4 RxFIFO mentioned here should be 4 TxFIFO on gateway destination side, right ?
regarding your problem “… experiencing MSGLST from a MO in the RXFIFO even though the FIFO is not full.” please see replies for in https://www.infineonforums.com/threa...4400-Multican?
each message object has 2 interrupt triggers (TxOk and RxOk interrupt). in case when a TxFIFO structure is used, the overflow interrupt (water level interrupt) of the TxFIFO base object is generated on RxOk interrupt of this base object, also 2 interrupt sources share on one interrupt trigger line.
extract from XMC user’s manual: If bit field MOFCRn.OVIE (“Overflow Interrupt Enable”) of the FIFO base object is set and the current pointer CUR becomes equal to MOFGPRn.SEL, a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt node RXINP of the base object after postprocessing of the received frame. Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set.
MSGLST indicates lost/or overwritten situation, but it can’t trigger interrupt.
the AppNote AP32300 has a detailed description about FIFO/Gateway with init. code, maybe it can help. https://www.infineon.com/dgdl/Infine...4ed91d6be32110
the 4 RxFIFO mentioned here should be 4 TxFIFO on gateway destination side, right ?
regarding your problem “… experiencing MSGLST from a MO in the RXFIFO even though the FIFO is not full.” please see replies for in https://www.infineonforums.com/threa...4400-Multican?
each message object has 2 interrupt triggers (TxOk and RxOk interrupt). in case when a TxFIFO structure is used, the overflow interrupt (water level interrupt) of the TxFIFO base object is generated on RxOk interrupt of this base object, also 2 interrupt sources share on one interrupt trigger line.
extract from XMC user’s manual: If bit field MOFCRn.OVIE (“Overflow Interrupt Enable”) of the FIFO base object is set and the current pointer CUR becomes equal to MOFGPRn.SEL, a FIFO overflow interrupt request is generated. The interrupt request is generated on interrupt node RXINP of the base object after postprocessing of the received frame. Receive interrupts are still generated for the Transmit FIFO base object if bit RXIE is set.
MSGLST indicates lost/or overwritten situation, but it can’t trigger interrupt.
the AppNote AP32300 has a detailed description about FIFO/Gateway with init. code, maybe it can help. https://www.infineon.com/dgdl/Infine...4ed91d6be32110