Hello All ,
Can any one please explain me how the STM(system timer logic works). i can understand it is a 64 bit timer and the value cannot be read in full so it is spitted into two registers. The interrupt generationof the tick is based on the compare and capture value of the timer.
I am not able to understand how the compare and capture register are acting producing counter at required rate(eg 1 ms). Please can you explain with an example especially the snapshots below(Fig 1 and Fig 2).
i will be really grateful to anyone providing me this explanation
Attachment 4272Attachment 4271nation.
Kind regards,
Deepak
Can any one please explain me how the STM(system timer logic works). i can understand it is a 64 bit timer and the value cannot be read in full so it is spitted into two registers. The interrupt generationof the tick is based on the compare and capture value of the timer.
I am not able to understand how the compare and capture register are acting producing counter at required rate(eg 1 ms). Please can you explain with an example especially the snapshots below(Fig 1 and Fig 2).
i will be really grateful to anyone providing me this explanation
Attachment 4272Attachment 4271nation.
Kind regards,
Deepak