Hello Support,
In the Aurix TC3xx User Manual 1.4 version,
"Separate ACCEN protection range for Safety Watchdog Timer" in Section 9.4.1.1 is mentioned.
Can you please provide me the corresponding details about which Registers this above line is referring so that I can understand better how Safety WDT can be accessed by a particular CPU in default state of ACCENxx register?
I am assuming by default any CPU can write to Safety WDT similar to Aurix TC2xx devices.
Thank you.
Regards
In the Aurix TC3xx User Manual 1.4 version,
"Separate ACCEN protection range for Safety Watchdog Timer" in Section 9.4.1.1 is mentioned.
Can you please provide me the corresponding details about which Registers this above line is referring so that I can understand better how Safety WDT can be accessed by a particular CPU in default state of ACCENxx register?
I am assuming by default any CPU can write to Safety WDT similar to Aurix TC2xx devices.
Thank you.
Regards