Hi Lucas,
This is the correct behaviour of the SPI RXEXIT register. The RXFIFO has a property that a read access from an empty RXFIFO generates an underflow interrupt, and delivers only “1” bits, which overrules the reset value.
Therefore reading from a non initialized RXFIFO delivers all “1” and not all ”0”.
Best regards,
Mr. AURIX™
This is the correct behaviour of the SPI RXEXIT register. The RXFIFO has a property that a read access from an empty RXFIFO generates an underflow interrupt, and delivers only “1” bits, which overrules the reset value.
Therefore reading from a non initialized RXFIFO delivers all “1” and not all ”0”.
Best regards,
Mr. AURIX™