In my application, I need to use four TLE5012, read through SPI.
Four chips, I use 1 CLK, 1 DATA, 4 CS connections.
A single one can be used normally. But when four are used together.
When one CS line is low and the rest are high, the DATA line will be forced to LOW. In other words, when CS is high, DATA is not the high resistance I want.
Why is that?
Four chips, I use 1 CLK, 1 DATA, 4 CS connections.
A single one can be used normally. But when four are used together.
When one CS line is low and the rest are high, the DATA line will be forced to LOW. In other words, when CS is high, DATA is not the high resistance I want.
Why is that?