November 27, 2018, 6:38 am
Alternative functionality of the pin is used in different purpose, which leads to the mentioned error after launching the debug. Now i have corrected the configuration of that particular pin, which resolved the issue.
thanks for your support.
--Anil Kumar. B
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November 27, 2018, 3:36 pm
Eric,
Any update to this? We're working on something and Sleep Mode registers are not readable because they are 16bit.
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November 27, 2018, 3:42 pm
XMC1404, using the code below. The lowest we've been able to get is 750uA with chip alone. Turned all IOs to inputs where we could, used another post here to get started. Having trouble figuring out what the chip could be using 500+uA extra over what the datasheet says we can expect. 5V VDD. Using only math, and CAN peripherals during normal use.
Code:
//Set all pins to inputs
XMC_GPIO_SetMode(XTAL1_PIN.gpio_port, XTAL1_PIN.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(XTAL1_PIN.gpio_port, XTAL1_PIN.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
XMC_GPIO_SetMode(XTAL2_PIN.gpio_port, XTAL2_PIN.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(XTAL2_PIN.gpio_port, XTAL2_PIN.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
XMC_GPIO_SetMode(BOOT0_PIN.gpio_port, BOOT0_PIN.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(BOOT0_PIN.gpio_port, BOOT0_PIN.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
XMC_GPIO_SetMode(UNUSED_PIN_0.gpio_port, UNUSED_PIN_0.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(UNUSED_PIN_0.gpio_port, UNUSED_PIN_0.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
XMC_GPIO_SetMode(UNUSED_PIN_1.gpio_port, UNUSED_PIN_1.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(UNUSED_PIN_1.gpio_port, UNUSED_PIN_1.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
... not all shown
XMC_GPIO_SetMode(UNUSED_PIN_21.gpio_port, UNUSED_PIN_21.gpio_pin, XMC_GPIO_MODE_INPUT_TRISTATE);
XMC_GPIO_SetInputHysteresis(UNUSED_PIN_21.gpio_port, UNUSED_PIN_21.gpio_pin, XMC_GPIO_INPUT_HYSTERESIS_STANDARD);
//Put pins in power save mode
XMC_GPIO_EnablePowerSaveMode(LED_PIN.gpio_port, LED_PIN.gpio_pin);
XMC_GPIO_EnablePowerSaveMode(XTAL1_PIN.gpio_port, XTAL1_PIN.gpio_pin);
XMC_GPIO_EnablePowerSaveMode(XTAL2_PIN.gpio_port, XTAL2_PIN.gpio_pin);
XMC_GPIO_EnablePowerSaveMode(BOOT0_PIN.gpio_port, BOOT0_PIN.gpio_pin);
XMC_GPIO_EnablePowerSaveMode(BOOT1_PIN.gpio_port, BOOT1_PIN.gpio_pin);
XMC_GPIO_EnablePowerSaveMode(UNUSED_PIN_0.gpio_port, UNUSED_PIN_0.gpio_pin);
... Not all shown
XMC_GPIO_EnablePowerSaveMode(UNUSED_PIN_21.gpio_port, UNUSED_PIN_21.gpio_pin);
//Turn off systick to prevent interrupts
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
// The clock of the peripherals that are not needed during sleep state can be gated before entering sleep state
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MATH);
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN);
// Enable FLASH power down during SLEEP and DEEPSLEEP mode
XMC_SCU_CLOCK_EnableFlashPowerDown();
// Make sure that SLEEPDEEP bit is set
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// Return to SLEEP mode after handling the wakeup event
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
// in deep-sleep state, the PCLK and MCLK will
// be switched to a slow standby clock and DCO1 will be put into power-down mode
// It is recommended to slow down the PCLK and MCLK before entering deep sleep
// mode to prevent a sudden load change that could cause a brownout reset.
XMC_SCU_CLOCK_SetFastPeripheralClockSource(XMC_SCU_CLOCK_PCLKSRC_MCLK);
XMC_SCU_CLOCK_SetMCLKFrequency(125);
// Put system in DEEPSLEEP state
__WFI();
}
Looking for things to try. This chip can't have a low potential of 750uA, that's way too high.
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November 28, 2018, 2:00 am
Hello everyone.
How does the gate monitoring function of 1 EDI 2002a S chip carry out simulation test? What's more,
does it compare the time of the rising or falling edge of the drive signal with the input, or does it refer to the voltage value of the drive signal ( because the specification says this )?
Best regards and thanks in advanceï¼
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November 28, 2018, 3:23 am
Hello,
we are using the ILLD (V1.0.1.8.0) for an Aurix TC275.
But we can't find any DMA support in the ILLD fort he ASC / SPI communication.
For other peripherals like QSPI there is an DMA support!
Is there a schedule to support DMA for ASC / SPI?
THX
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November 28, 2018, 11:27 am
Hello!
I was wondering if has anyone with some experience in high current projects using BTN8982TA.
At my company we are developing a platform elevator, which we have to control a 500w, 24V DC motor. This platform, in max load, can draw 30Amps.
Until yesterday we were experiencing some sucess in BTN board, but, during the test cycles in our client, one of the BTN blow up and also our controller board. The controller board was damaged because of the IS pin of the BTN, it somehow was in 24V and my controller board couldn't manage this high voltage.
We are looking for the problem, but no sucess until now, and I've researched through the internet to see if someone has a similar experience with BTN8982. Because of this I decided to create this forum, to see if somene maybe infineon itself has any advice in high power projects using BTN8982.
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November 28, 2018, 2:25 pm
I was looking for some tech. specs. summary like max recommended ESR for the crystal etc...
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November 28, 2018, 6:20 pm
It looks like there is a bug in the HW_Init code in "Dave/Generated/ECAT_SSC/xmc_eschw.c"
The gpio_config and port_control structures are not being fully initialized. This results in the gpio_config.output_level variable being assigned a random stack value.
When gpio_config.output_level is used to initialize the ECAT gpios in XMC_GPIO_Init() it assigns garbage stack values into the OMR register.
port->OMR = (uint32_t)config->output_level << pin;
UINT16 HW_Init(void)
{
uint8_t i;
XMC_ECAT_PORT_CTRL_t port_control;
XMC_GPIO_CONFIG_t gpio_config;
memset(&port_control, 0, sizeof(port_control)); // <-- add this line
memset(&gpio_config, 0, sizeof(gpio_config)); // <-- add this line
============================
DAVE Version: 4.4.2
ECAT_SSC APP Version: 4.0.22
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November 28, 2018, 11:36 pm
Unfortunately the provided files do not help to follow the interrupt chain.
You need to verify the following:
1) Is the interrupt event generated inside the GTM? This means: Is the timer correctly set up? Is is counting? Do the event flags get set? Is the interrupt flag set? Search for registers name IRQ_NOTIFY
2) Is the interrupt routed to the correct service provider (CPUx?): Check the corresponding SRC_xxxx Register. The correct register you can find in the Interrupt Router-chapter of the user manual.
3) Do the interrupt Service Request Priority Number (SRPN) in the SRC register and the number of the interrupt service routine in the interrupt table matching? Usually defined whith the definition of the ISR.
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November 29, 2018, 2:03 am
Hi to all.
I've found many answsers to similar questions, but none of the worked for my case.
Maybe because the IDE was older or the processor was not the same.
Can someone give me a step of actions I must perform to reach the target into the title?
Or even better to redirect the output to a Telnet connection for external tools.
Thank you.
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November 27, 2018, 5:38 am
Hey there,
I can't figure out how the Distance2Go processes I and Q data to get values for both range and speed within a single (or multiple?) measurement. What I know from theory so far is that you usually need a sequence of transmitted chirps (at least 2) to be able to resolve for both range R and speed v (or Doppler frequency fD).
Theory says this is done via a range-doppler-matrix and a two-dimensional FFT. But is that the case with the D2G board as well? I'm reading through the source code in DAVE but I did not figure that out yet. I stumbled across some 'mean' calculations, what to they do?
How can the board determine range and speed I if set the number of chirps to '1'?
In algo_api.h it is said: "Currently a single FMCW and a Doppler chirp is generated within a single frame." What does that mean?
Another question is the correlation between number of chirps, samples per chirp, data size and frame time.
As far as I understand it:
Number of chirps is the number of chirps that is generated within one frame.
Samples per chirp is equivalent to the number of samples per chirp, so if I'd have 2 chirps I need to store or evaluate 2 times the data.
Data size is the hardware buffer size (max 250)? So if I have 2 chirps and 250 samples per chirp, it evaluates the 250 samples from the first and after that the next 250 samples from the second chirp?
Frame time or minimum frame time is the time required to generate upchirp and downramp (limited by various hardware), e.g. ramp down time (PLL) and the time it takes to perform the calculations (algorithm process time etc). So I should get errors when setting the frame time lower that the minimum frame time.
I'd like to understand the system more, especially I'd like to learn about the resolution process of range and speed. Are there any sources I can get more information? I appreciate any help!
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November 28, 2018, 3:23 am
Hello,
we are using the ILLD (V1.0.1.8.0) for an Aurix TC275.
But we can't find any DMA support in the ILLD fort he ASC / SPI communication.
For other peripherals like QSPI there is an DMA support!
Is there a schedule to support DMA for ASC / SPI?
THX
↧
November 28, 2018, 6:20 pm
It looks like there is a bug in the HW_Init code in "Dave/Generated/ECAT_SSC/xmc_eschw.c"
The gpio_config and port_control structures are not being fully initialized. This results in the gpio_config.output_level variable being assigned a random stack value.
When gpio_config.output_level is used to initialize the ECAT gpios in XMC_GPIO_Init() it assigns garbage stack values into the OMR register.
port->OMR = (uint32_t)config->output_level << pin;
UINT16 HW_Init(void)
{
uint8_t i;
XMC_ECAT_PORT_CTRL_t port_control;
XMC_GPIO_CONFIG_t gpio_config;
memset(&port_control, 0, sizeof(port_control)); // <-- add this line
memset(&gpio_config, 0, sizeof(gpio_config)); // <-- add this line
============================
DAVE Version: 4.4.2
ECAT_SSC APP Version: 4.0.22
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November 27, 2018, 5:38 am
Hey there,
I can't figure out how the Distance2Go processes I and Q data to get values for both range and speed within a single (or multiple?) measurement. What I know from theory so far is that you usually need a sequence of transmitted chirps (at least 2) to be able to resolve for both range R and speed v (or Doppler frequency fD).
Theory says this is done via a range-doppler-matrix and a two-dimensional FFT. But is that the case with the D2G board as well? I'm reading through the source code in DAVE but I did not figure that out yet. I stumbled across some 'mean' calculations, what to they do?
How can the board determine range and speed I if set the number of chirps to '1'?
In algo_api.h it is said: "Currently a single FMCW and a Doppler chirp is generated within a single frame." What does that mean?
Another question is the correlation between number of chirps, samples per chirp, data size and frame time.
As far as I understand it:
Number of chirps is the number of chirps that is generated within one frame.
Samples per chirp is equivalent to the number of samples per chirp, so if I'd have 2 chirps I need to store or evaluate 2 times the data.
Data size is the hardware buffer size (max 250)? So if I have 2 chirps and 250 samples per chirp, it evaluates the 250 samples from the first and after that the next 250 samples from the second chirp?
Frame time or minimum frame time is the time required to generate upchirp and downramp (limited by various hardware), e.g. ramp down time (PLL) and the time it takes to perform the calculations (algorithm process time etc). So I should get errors when setting the frame time lower that the minimum frame time.
I'd like to understand the system more, especially I'd like to learn about the resolution process of range and speed. Are there any sources I can get more information? I appreciate any help!
↧
November 28, 2018, 3:23 am
Hello,
we are using the ILLD (V1.0.1.8.0) for an Aurix TC275.
But we can't find any DMA support in the ILLD fort he ASC / SPI communication.
For other peripherals like QSPI there is an DMA support!
Is there a schedule to support DMA for ASC / SPI?
THX
↧
November 28, 2018, 6:20 pm
It looks like there is a bug in the HW_Init code in "Dave/Generated/ECAT_SSC/xmc_eschw.c"
The gpio_config and port_control structures are not being fully initialized. This results in the gpio_config.output_level variable being assigned a random stack value.
When gpio_config.output_level is used to initialize the ECAT gpios in XMC_GPIO_Init() it assigns garbage stack values into the OMR register.
port->OMR = (uint32_t)config->output_level << pin;
UINT16 HW_Init(void)
{
uint8_t i;
XMC_ECAT_PORT_CTRL_t port_control;
XMC_GPIO_CONFIG_t gpio_config;
memset(&port_control, 0, sizeof(port_control)); // <-- add this line
memset(&gpio_config, 0, sizeof(gpio_config)); // <-- add this line
============================
DAVE Version: 4.4.2
ECAT_SSC APP Version: 4.0.22
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November 29, 2018, 12:14 pm
Interested to know whether compliant to frameworks like AUTOSAR or certified or not. I know Infineon offers the (free) iLLD set and the (not free) MCAL/MC-ISAR set, so I'm wondering about others.
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November 30, 2018, 12:29 am
hi,
I tried according to your calculations and following value are obtained:
For 10 ms =0x3D09
For 20 ms =0x3D09
For 50 ms =0x1312D
For 100 ms =0x1312D
but when I changed respective values in my code, same task is getting called at variable time and that time in more than 10 sec always.
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November 30, 2018, 1:36 am
Hi,
can you please check if you switched your slave into freerun-state?
For toggling freerun-state see slide 55 (TwinCAT3) and slide 46 (TwinCAT2) inside docu XMC43/3.1.
Only if you switched your device into freerun-state the slave can go into operational.
Kind Regards
Michael
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November 30, 2018, 7:31 am
Hi,
I am looking into the possibility of using the FCE peripheral in 32-bit CRC mode to validate application code stored in PFlash. The application code will contain its CRC value that is calculated at link time using the Tasking linker checksum algorithm which is also used to create the boot mode header (BMHD) CRC values. I can successfully get the linker to create a 32-bit CRC over a specified flash memory range and embed this value to a known location; I can also get the FCE to calculate its CRC over this same range but the two CRC's differ. I am still trying to understand why they are not the same and have even limited the address range to a single 32-bit value. I notice in the FCE and linker documentation, the former refers to using a polynomial of 0x04C11DB7 and the latter a polynomial of 0xEDB88320; apparently one is the reversed polynomial of the other. Does this render using the FCE and linker CRC calculations incompatible with each other? i.e. will they always return different CRC's?
Any help/suggestions much appreciated.
Regards
Richard
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