Hi,
could you please explain the advantage of Kelvin emitter of IGBTs?
Thank you in advance!
could you please explain the advantage of Kelvin emitter of IGBTs?
Thank you in advance!
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Kelvin emitter
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Switching 1500Vdc/10A
We work in the photovoltaic industry and need to test 24 module strings, operating at 1500Vdc./10A. In order to perform the tests, we have a 1500Vdc 15kW power supply, run from a generator, that will be connected to one string at a time and would need to switch between strings remotely (wireless).
The 24 channels would need to be switch LIVE, as wee will not be able switch the power supply on and off remotely.
Would it be possible to source SSR's/Mosfet's/IGBT's that would be able to switch the voltage and current required?
Assistance with specifying the components required, circuit and PCB board design would be greatly appreciated.
Regards
The 24 channels would need to be switch LIVE, as wee will not be able switch the power supply on and off remotely.
Would it be possible to source SSR's/Mosfet's/IGBT's that would be able to switch the voltage and current required?
Assistance with specifying the components required, circuit and PCB board design would be greatly appreciated.
Regards
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Tag Connect
Presently using Tag Connects on all of our XMC4000 series boards. Works great!
Looking for something similar for XMC1000 series boards.
Looking for something similar for XMC1000 series boards.
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Thermal paste for 62 mm, too?
I am wondering if the 62 mm modules are available with thermal paste?
Thanks for help.
Thanks for help.
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IGBT gate voltage and short-circuit-mode
Hi guys, quick question, why would it be advantageous to lower IGBT gate voltage in short circuit mode?
Thanks!
Thanks!
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Looking for the XC164CM UCAN Starter kit USB stick
This is really good stuff for a junk hauling company
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TLE82453 setpoint value
hello all
Greeting for the day, i am working on TLE82453 chip set device for controlling the load and the micro controller i am using to communicate Infineon TC277.
I am trying to set the setpoint register value and the PWM period value. i would like to request set point formula to derive the target current and also PWM period calculations related to setpoint target current.
Currently I am calculating using the below method.
To set target current 250mA, 250mA = x * lsb ----> lsb = (1500/2047)mA
x = 341 approx.
when i set the x as a set point value, I am reading the current as 700mA but not 250mA.
Kindly shed your thoughts on it.
Kind Regards,
Deepak
Greeting for the day, i am working on TLE82453 chip set device for controlling the load and the micro controller i am using to communicate Infineon TC277.
I am trying to set the setpoint register value and the PWM period value. i would like to request set point formula to derive the target current and also PWM period calculations related to setpoint target current.
Currently I am calculating using the below method.
To set target current 250mA, 250mA = x * lsb ----> lsb = (1500/2047)mA
x = 341 approx.
when i set the x as a set point value, I am reading the current as 700mA but not 250mA.
Kindly shed your thoughts on it.
Kind Regards,
Deepak
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SSC files for XMC4800
Hi ,
I have this kit
https://www.digikey.com/product-deta...BO1-ND/9816150
and i'm trying to follow the training here https://www.infineonforums.com/threa...4800-relax-kit
but i don't have the generated files from from the slave stack code as i'm not a member of the ETG and i couldn't get the membership , any other solution or this ? Is there another source to get this filels ?
can i find opensource implementation ?
Thank you .
I have this kit
https://www.digikey.com/product-deta...BO1-ND/9816150
and i'm trying to follow the training here https://www.infineonforums.com/threa...4800-relax-kit
but i don't have the generated files from from the slave stack code as i'm not a member of the ETG and i couldn't get the membership , any other solution or this ? Is there another source to get this filels ?
can i find opensource implementation ?
Thank you .
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I changed the PLL clock from 200MHZ to 300MHZ and my code doesn't run anymore
Hi Bernie,
A potential reason for such issue is the configured Flash Wait Cycles which depend on the configured clock. Please configure the Flash Wait Cycles according to the calculation provided in the user manual.
Best regards,
Mr. AURIX™
A potential reason for such issue is the configured Flash Wait Cycles which depend on the configured clock. Please configure the Flash Wait Cycles according to the calculation provided in the user manual.
Best regards,
Mr. AURIX™
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Debugging ADC with no HW Trigger Present
Hi Christine,
Yes, you can start conversions by software, e.g. for verify an ADC configuration without a proper HW Trigger. This is often the case when you are debugging to find the root source of ADC conversion issues. In the case of AURIX™ TC2XX, for Scan and
Background Scan, each request source has a LDEV (GxASMR.LDEV=1 and BRSMR.LDEV=1) bit that can load the ADC request source. And for queues, there is a TREV field (GxQMRy.TREV=1) that can be used to load this type of request source.
Best regards,
Mr. AURIX™
Yes, you can start conversions by software, e.g. for verify an ADC configuration without a proper HW Trigger. This is often the case when you are debugging to find the root source of ADC conversion issues. In the case of AURIX™ TC2XX, for Scan and
Background Scan, each request source has a LDEV (GxASMR.LDEV=1 and BRSMR.LDEV=1) bit that can load the ADC request source. And for queues, there is a TREV field (GxQMRy.TREV=1) that can be used to load this type of request source.
Best regards,
Mr. AURIX™
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GTM HW Trigger to ADC, Rising/Falling Edge from GTM
Hi Christine,
When triggering VADC from GTM, it is common to use triggering (edges) as opposed to gating (levels). The VADC "sees" the signal level of the GTM. So if the signal level changes from low to high, this is associated with rising edge trigger, and vice versa for falling edge. It is important, in this case, to account for the GTM signal level ((A)TOMi_CHx_CTRL.SL) in order to determine where the ADC is triggered. Often it is the case where the VADC specific (A)TOM channel is not routed externally, but internal only. It must be accounted and verified edge placement of rising and falling edges.
Best regards,
Mr. AURIX™
When triggering VADC from GTM, it is common to use triggering (edges) as opposed to gating (levels). The VADC "sees" the signal level of the GTM. So if the signal level changes from low to high, this is associated with rising edge trigger, and vice versa for falling edge. It is important, in this case, to account for the GTM signal level ((A)TOMi_CHx_CTRL.SL) in order to determine where the ADC is triggered. Often it is the case where the VADC specific (A)TOM channel is not routed externally, but internal only. It must be accounted and verified edge placement of rising and falling edges.
Best regards,
Mr. AURIX™
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Which pin default state is defined by HWCFG6?
Hi Christine,
Please refer to "Legend" of "Package and Pinning Definitions" on the data sheet (DS).
The default state of a pin which has "PU1" or "PD1" in the column "Type" is defined by HWCFG6.
In actual, there would be no device which has a pin with "PD1".
Best regards,
Mr. AURIX™
Please refer to "Legend" of "Package and Pinning Definitions" on the data sheet (DS).
The default state of a pin which has "PU1" or "PD1" in the column "Type" is defined by HWCFG6.
In actual, there would be no device which has a pin with "PD1".
Best regards,
Mr. AURIX™
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I2S support with the Aurix
Hi Lucas,
The Aurix does not have a dedicated I2S HW-module, but there is the possibilities to emulate I2S master and slave.
Master: For generating an I2S output, where the Aurix is the master the Queued SPI (QSPI) module can be used. To do so use the QSPI in simplex mode transmit mode. You will need two chip selects (SLSO), one for left/right and the second one as a dummy. The chip-select can be switched using the BACON entries.
Slave: In the slave mode the Aurix is responsible to receive the sound signals from an external master. To do so the Timer Input channels (TIM) of the Generic Timer Module (GTM) are used. E.g. TIM_0 is detecting the right or left noise while. TIM_1 is responsible to track the clock and trigger TIM_2 at a rising clock edge. TIM_2 will then track the data and store them through the ARU in the FIFO. By reaching the defined watermark in the FIFO the DMA is triggered to transfer the data to the memory.
Best regards,
Mr. AURIX™
The Aurix does not have a dedicated I2S HW-module, but there is the possibilities to emulate I2S master and slave.
Master: For generating an I2S output, where the Aurix is the master the Queued SPI (QSPI) module can be used. To do so use the QSPI in simplex mode transmit mode. You will need two chip selects (SLSO), one for left/right and the second one as a dummy. The chip-select can be switched using the BACON entries.
Slave: In the slave mode the Aurix is responsible to receive the sound signals from an external master. To do so the Timer Input channels (TIM) of the Generic Timer Module (GTM) are used. E.g. TIM_0 is detecting the right or left noise while. TIM_1 is responsible to track the clock and trigger TIM_2 at a rising clock edge. TIM_2 will then track the data and store them through the ARU in the FIFO. By reaching the defined watermark in the FIFO the DMA is triggered to transfer the data to the memory.
Best regards,
Mr. AURIX™
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can we write data into Pflash even if the address is written with 0X00?
Hi Lucas,
Yes, you can successful write data into Pflash even if this address already written with data 0x00, but it will generate an ECC error because the new ECC value can't be programmed properly. This will cause a correctable or uncorrectable ecc error on the page of the address.
Always erase the sector before you write any value to avoid wrong ECC values and errors.
Best regards,
Mr. AURIX™
Yes, you can successful write data into Pflash even if this address already written with data 0x00, but it will generate an ECC error because the new ECC value can't be programmed properly. This will cause a correctable or uncorrectable ecc error on the page of the address.
Always erase the sector before you write any value to avoid wrong ECC values and errors.
Best regards,
Mr. AURIX™
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Why PORST voltage level after PORST release is a bit lower than VEXT(e.g. 5V)?
Hi Lina,
There is a weak pull-down internally in the PORST pad. It is for keeping PORST weakly pulled low in case of bond wire breakage. The pull down is inactive to avoid additional current during STANDBY mode.
Best regards,
Mr. AURIX™
There is a weak pull-down internally in the PORST pad. It is for keeping PORST weakly pulled low in case of bond wire breakage. The pull down is inactive to avoid additional current during STANDBY mode.
Best regards,
Mr. AURIX™
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How to inject faults in Pflash of AURIX TC2xx microcontrollers ?
Hi Lina,
You can inject faults in PFlash following this method:
1- The ECC code causing the required error type (e.g. triple-bit error) can be determined
by first programming the data with automatic ECC generation on.
2- Read this programmed data to find the corresponding ECC code in ECCRPp.RCODE.
3- Switch OFF automatic ECC generation: ECCW.PECENCDIS = 1.
4- Write the value of ECC code (obtained in step 2- in in ECCRPp.RCODE) into ECCW.WCODE.
5- Now, generate the bit errors in the data to program by setting additional bit(s) in the read data.
6- Reprogram the page with this data.
Best regards,
Mr. AURIX™
You can inject faults in PFlash following this method:
1- The ECC code causing the required error type (e.g. triple-bit error) can be determined
by first programming the data with automatic ECC generation on.
2- Read this programmed data to find the corresponding ECC code in ECCRPp.RCODE.
3- Switch OFF automatic ECC generation: ECCW.PECENCDIS = 1.
4- Write the value of ECC code (obtained in step 2- in in ECCRPp.RCODE) into ECCW.WCODE.
5- Now, generate the bit errors in the data to program by setting additional bit(s) in the read data.
6- Reprogram the page with this data.
Best regards,
Mr. AURIX™
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Can you provide the latest stencils for TriBoard Extension-Board?
Hi Lina,
It's already contained at StarterKIT. If needed you can download from the AURIX documentation in myicp-dmz.extra.infineon.com. Please print and cut it by yourself.
Best regards,
Mr. AURIX™
It's already contained at StarterKIT. If needed you can download from the AURIX documentation in myicp-dmz.extra.infineon.com. Please print and cut it by yourself.
Best regards,
Mr. AURIX™
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Why many Pflash ECC errors are reported on HT test while RT/LT tests are ok?
Hi Lucas,
Check flash waitstate if it is enough to cover the access delay by PMU_FCON.WSPFLASH. The default setting is calculated with lower fFSI. with higher fFSI, you need to configure more waitstates.
Best regards,
Mr. AURIX™
Check flash waitstate if it is enough to cover the access delay by PMU_FCON.WSPFLASH. The default setting is calculated with lower fFSI. with higher fFSI, you need to configure more waitstates.
Best regards,
Mr. AURIX™
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XMC4800 receive interrupt
Hi,
You need to enable the USIC channel to generate interrupts.
If you're using the Infineon UART app code, you can call the UART_StartReceiveIRQ() routine.
If you want to handle all the buffering on your own, you can simply call:
XMC_USIC_CH_EnableEvent(handle->channel, (uint32_t)((uint32_t)XMC_USIC_CH_EVENT_STANDARD_RE CEIVE | (uint32_t)XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE));
Note that the call above does not use the USIC FIFO If you want to use the USIC FIFO, see the code inside UART_StartReceiveIRQ() for how to handle the FIFO.
rgds,
Gary
You need to enable the USIC channel to generate interrupts.
If you're using the Infineon UART app code, you can call the UART_StartReceiveIRQ() routine.
If you want to handle all the buffering on your own, you can simply call:
XMC_USIC_CH_EnableEvent(handle->channel, (uint32_t)((uint32_t)XMC_USIC_CH_EVENT_STANDARD_RE CEIVE | (uint32_t)XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE));
Note that the call above does not use the USIC FIFO If you want to use the USIC FIFO, see the code inside UART_StartReceiveIRQ() for how to handle the FIFO.
rgds,
Gary
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I2C on smaller devices like AURIX TC23x, TC22x and TC21x
You should consider using a SPI-to-I2C bridge, like this one.
https://www.nxp.com/docs/en/data-sheet/SC18IS600.pdf
https://www.nxp.com/docs/en/data-sheet/SC18IS600.pdf
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