#define RXD1 P14_9
#define RXD0 P14_8
#define RXER P0_11
#define CLK_RMII P15_8
#define TX_EN P5_9
#define TXD1 P2_13
#define TXD0 P2_12
#define CRS_DV P15_9
#define MDIO P1_11
#define MDC P1_10
low_level_init(struct netif *netif)
{
port_control.mode = XMC_ETH_MAC_PORT_CTRL_MODE_RMII;
port_control.rxd0 = XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8;
port_control.rxd1 = XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9;
port_control.clk_rmii = XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8;
port_control.crs_dv = XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9;
port_control.rxer = XMC_ETH_MAC_PORT_CTRL_RXER_P0_11;
port_control.mdio = XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11;
XMC_ETH_MAC_SetPortControl(ð_mac, port_control);
XMC_ETH_MAC_Init(ð_mac);
XMC_ETH_MAC_DisableJumboFrame(ð_mac);
gpio_config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
gpio_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL |P2_12_AF_ETH0_TXD0);
XMC_GPIO_Init(TXD0, &gpio_config);
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_13_AF_ETH0_TXD1);
XMC_GPIO_Init(TXD1, &gpio_config);
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P5_9_AF_ETH0_TX_EN);
XMC_GPIO_Init(TX_EN, &gpio_config);
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P1_10_AF_ETH0_MDC);
XMC_GPIO_Init(MDC, &gpio_config);
XMC_GPIO_SetHardwareControl(MDIO, XMC_GPIO_HWCTRL_PERIPHERAL1);
}Load "C:\\Files\\Projects\\MDK\\XMC1400_Test_JLINK\\Objects\\XMC1400_Test_JLINK.axf"
Set JLink Project File to "C:\Files\Projects\MDK\XMC1400_Test_JLINK\JLinkSettings.ini"
* JLink Info: Device "XMC1404-0200" selected.
JLink info:
------------
DLL: V6.62d, compiled Mar 2 2020 09:22:41
Firmware: J-Link Lite-XMC4200 Rev.1 compiled Mar 1 2019 11:28:26
Hardware: V1.00
S/N : 591046198
* JLink Info: Trying to identify target via SPD
* JLink Info: Could not identify target via SPD. Trying again via SWD.
* JLink Info: Found SW-DP with ID 0x0BB11477
* JLink Info: Unknown DP version. Assuming DPv0
* JLink Info: Scanning AP map to find all available APs
* JLink Info: AP[1]: Stopped AP scan as end of AP map has been reached
* JLink Info: AP[0]: AHB-AP (IDR: 0x04770021)
* JLink Info: Iterating through AP map to find AHB-AP to use
* JLink Info: AP[0]: Core found
* JLink Info: AP[0]: AHB-AP ROM base: 0xF0000000
* JLink Info: CPUID register: 0x410CC200. Implementer code: 0x41 (ARM)
* JLink Info: Found Cortex-M0 r0p0, Little endian.
* JLink Info: FPUnit: 4 code (BP) slots and 0 literal slots
* JLink Info: CoreSight components:
* JLink Info: ROMTbl[0] @ F0000000
* JLink Info: ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB471 ROM Table
* JLink Info: ROMTbl[1] @ E00FF000
* JLink Info: ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
* JLink Info: ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
* JLink Info: ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
ROMTableAddr = 0xF0000000
* JLink Info: Performing XMC1000 reset
Target info:
------------
Device: XMC1404-Q064x0200
VTarget = 3.300V
State of Pins:
TCK: 0, TDI: 0, TDO: 0, TMS: 16, TRES: 0, TRST: 1
Hardware-Breakpoints: 4
Software-Breakpoints: 8192
Watchpoints: 2
JTAG speed: 3000 kHz
Erase Done.
Programming Done.
Verify OK.
Flash Load finished at 15:19:02