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TC223 PFLASH Programming

November 20, 2020, 7:01 am
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Hello,

I am trying to program a pflash area on the TC223. I already did successful program an area in the dflash. The GitHub Project was a good guide: https://github.com/Infineon/AURIX_co..._KIT_TC297_TFT

However when programming the pflash I always get stuck with a Protection Error. I already checked a bunch of registers, but I do not see a bit indicating that I am not allowed to erase or write in the pflash, see screenshot below.
Attachment 5302

I also did use the memcopy operations for the flash commands, to copy them into the SRAM. I was wondering if I should also copy other functions of my code into the sram to not disturb the pflash with reads when trying to program. Do I need to do that although I am programming a different sector where none of my code is lying?

Any guidance is appreciated!
Alex
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SAF-XC167CI-32F40F BB-A IBIS model

November 20, 2020, 7:48 am
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Hello all,
I am working on a new project, using SAF-XC167CI-32F40F BB-A mcu. For simulating purposes I will be needing an IBIS model of this device. Does anyone had experienced a similar issue, and if so, how he has went thru it ?
Also , it could not be exactly the same MCU, mentioned above, but an IBIS model of a close in parameters MCU would help also a lot.

Thanks!
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Distance2Go Doppler and FMCW mode (range and speed)

November 21, 2020, 7:05 am
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Hi everyone,

I am thinking of using Distance2Go to measure distance. Could someone please let me know how to program Distance2go demo board to create 2 GHz FMCW bandwidth, thanks.
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The issue about QSPI communication with TFT

November 21, 2020, 7:32 am
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Hi
Can you please tell me which IDE you have used for initializing TFT LCD?
I am using Aurix IDE, but unable to lit my LCD. I don't have any sample code.
My hardware is TC387QP.

If you have any sample code for that for Aurix IDE, can you please share it with me?

Thanks in advance.

Quote:
Originally Posted by ljs6040 View Post
Hello, everyone.

I have tried to work TFT lcd on TC237 app-kit since 2 weeks ago.
I have used the demo code for TC237 app-kit which is provided from infineon.
It has worked well. but I only wanna extract the code for operating TFT because of My project.
So, I have tried to extract TFT function codes from the demo files.

However, My TFT has displayed continuous thin black lines like below.
I copied and pasted this exact same codes on new project for TFT test.
I think it has QSPI communication problems by unknown errors. but I have exactly copied the TFT code work-well .

Please give me your opinion about this problem.
How can I solve this problem?

Attachment 5278
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J-Link GDB Server failed: Could not listen on tcp port. Please check if another vers

November 21, 2020, 11:45 am
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I'm seeking help from expert on this issue. I have DAVE 4.4.2 and use it for XMC4700-F100x2048. The debugger used to work for the device.
There is one day I dont' have wifi on the computer. I tried to use the Debugger, it has problems. When the wifi comes back, it still does not work.

I tried to reinstall Dave, and Segger J-Link. It did not help.

Here are the details I got in the Console window.


J-Link is connected.
Firmware: J-Link Lite-XMC4200 Rev.1 compiled Mar 1 2019 11:28:26
Hardware: V1.00
S/N: 599002341
Checking target voltage...
Target voltage: 3.30 V
ERROR: Failed to listen at socket (Err = -1)
ERROR: Failed to open listener port 2331
Restoring target state and closing J-Link connection...
Shutting down...

Thank you in advance for any suggestion!
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Need a substitute for IR3895MTRPBF and IR3827MTRPBF

November 22, 2020, 3:24 am
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Hi,

We are designing new hardware for IMX8QM SoC. For that IR3895MTRPBF and IR3827MTRPBF are some ICs that should use for our design.
But seems that they are in End of Life state in the production process. So could you please let me know the substitute part numbers for IR3895MTRPBF and IR3827MTRPBF ?

Thanks
Ashan
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Tolerance/Deviation of Peripheral PLL (fpll1) - TC377TP

November 22, 2020, 2:29 pm
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Quote:
Originally Posted by UC_wrangler View Post
Check out Table 3-37 PLL Peripheral in the datasheet.

"Peak accumulated jitter" is +/- 700 ps. The accumulated jitter over a single bit time interval (e.g., 500 ns @ 2 Mbps) is a little less than that - see application note AP32390 for a discussion of short-term and long-term jitter.

Of course, that needs to be added to the variation of the external oscillator, which is typically something like 300 ppm.
I went through AP32390. From AP32390 it looks like using PLL as clock source for CAN Baud Rate generation is not a good idea.
Is my understanding correct or am I missing something ?

In my past experience in using TC2xx devices, we were recommended to not use PLL as clock source for CAN. I am assuming this is true even for TC3xx devices. Any thoughts ?
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TLE987X BLDC_SENSORLESS_FOC/Current sensing/ CSA gain computation

November 22, 2020, 5:38 pm
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Hi,
You can refer to the the chapter of CSA in Manual,you will find the limitation of CSA differential input voltage is 1.5V.
1.25V is secured OpAmp differential input voltage range .
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TLE9879 Eval Kit Hall Sensor Discrepancies

November 22, 2020, 5:47 pm
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Hi,
No matter the suqence of ABC.In Hall register, the sequence of Hall signal is CCPOS2 CCPOS1 CCPOS0.
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TLE9879 active braking a BLDC Motor

November 22, 2020, 5:57 pm
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Hi,
First,you shoud set the 3 Bridge Low Side Drivers to State PWM,then set the MCMOUT rigister to active the 3 Bridge Low Side Drivers.This method will avoid overcurrent protection.The operation of MCMOUT register,you can refer to the HALL commutaion table.
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BLDC_SENSORLESS_FOC_LIN_EXAMPLE_TLE987X / Clarification of some variables

November 22, 2020, 6:12 pm
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Hi,
These values are part of Infineon FOC algorithm.I guess only the Infineon engineer know the real meaning of these value.But you can find some clues in the figure below.
Attachment 5303
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Address of the peripherals on tle9879

November 22, 2020, 6:18 pm
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Hi,
You can quickly find all TLE9879's register details in tle987x.h file.
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use yocto linux for project development

November 23, 2020, 12:10 am
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Hi there ,
Can yocto linux be used on xmc4500 relax kit for gui project?
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HOST and HSM accessing Their D Flashs Simultaneously on TC39x

November 23, 2020, 1:22 am
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There was an access of CPU0 to DAM0 RAM1, I expect here from the firmware of the device. This has nothing to do with your trap. Your trap comes from a read access to DF0 address 0xAF011120. This access returned an error. Maybe CPU0 would read the address but the HSM wrote to this location at the same time. Is there any error on HSM?.
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BTN8982TA easy to burn...

November 23, 2020, 7:03 am
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I have a problem with BTN8982TA H-Bridge - when I change the direction of of the motor until it stops his movement - I have two IC's burned.

Attachment 5304
Attachment 5305

I just put 24V power supply, and PWM is constant 0, INA & INB pulled up. I Start the motor by giving 1 on PWM and 0 on (for example) INA. When I put 1 on INA and 0 pn PWM the motor is freewheeling.
If I don't wait until the motor stops his movement and I put 1 on INB (opposite direction) and 1 on PWM - both drivers are burned.

I checked - if I have 2Ohm resistore instead of motor the problem doesn't exist.
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MBIST running on HSM core

November 23, 2020, 7:25 am
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Hello,

is it valid to test a specific memory in HSM using MBIST? e.g the memory shared between the tricore and HSM is used during tricore startup, so MBIST cannot test the used memory directly without handshaking with HSM, so my question is it valid to test this memory in HSM since the HSM is connected to the SPB bus so it is allowed to access the MTU? and is there any problems from such scenario?
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How to configure DMA channel for ADC results

November 23, 2020, 10:00 am
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If I configured ADC interrupts to be handle by DMA, the configuration parameters in DMA how should I choose the configuration parameters, to what are they related? ADC configuration or how can I make sure it is correctly configured to work properly.
Because currently I configured a destination address for the results of ADC to be written in, the DMA is overwriting in address before the defined address in the destination address and trashing these areas before the destination
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iLLD Linking problem – Tasking

November 23, 2020, 2:12 pm
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Dear Forum Members,

I downloaded below version of iLLD package from Infineon (version 1.11.0) and trying to port the example to Tasking compiler and I am running into below error.

- iLLD_1_0_1_11_0__TC37A
- iLLD_1_0_1_11_0__TC3xx_Demos/GtmAtomPwmHlDem

I am using TC377TP MCU and want to port ATOM demo to tasking compiler (Version: 6.3r1).
I have chosen to use the startup files included in “iLLD_1_0_1_11_0__TC37A” instead of generating the startup files from Tasking. I prefer to use the startup files from Infineon instead of Tasking for my application.

I am able to compile all the files correctly, however I am running into below linking problem.
I reviewed the linker file of Tasking and the symbol names are different. Does anyone have the linker file that works with this configuration ?

ltc E106: unresolved external: __USTACK0 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __CSA0 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __ISTACK0 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __CSA0_END - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __START1 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __TRAPTAB_CPU0 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __INTTAB_CPU0 - (Ifx_Ssw_Tc0.o)
ltc E106: unresolved external: __USTACK1 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __TRAPTAB_CPU1 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __INTTAB_CPU1 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __ISTACK1 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __INTTAB_CPU2 - (Ifx_Ssw_Tc2.o)
ltc E106: unresolved external: __CSA1 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __CSA1_END - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __START2 - (Ifx_Ssw_Tc1.o)
ltc E106: unresolved external: __USTACK2 - (Ifx_Ssw_Tc2.o)
ltc E106: unresolved external: __TRAPTAB_CPU2 - (Ifx_Ssw_Tc2.o)
ltc E106: unresolved external: __ISTACK2 - (Ifx_Ssw_Tc2.o)
ltc E106: unresolved external: __CSA2 - (Ifx_Ssw_Tc2.o)
ltc E106: unresolved external: __CSA2_END - (Ifx_Ssw_Tc2.o)
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Can't add CMSIS_RTOS_RTX5 app instance

November 23, 2020, 3:07 pm
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Hi Jesus,

Thank you very much. The problem is fixed.
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Safe operating area for FF23MR12W1M1P_B11

November 23, 2020, 11:39 pm
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Hi there,

We are developing a 50kW three phase inverter using 4Si/2SiC ANPC converter and are evaluating various SiC mosfets.
Based on the ratings, FF23MR12W1M1P_B11 looks like a good fit. However, the datasheet does not provide much information. Our main concern is the safe operating area of this module.
The datasheet only gives RBSOA while we know nothing about FBSOA about this module. Based on our current design, the mosfet will be switched on and off at 700V (maximum) with a peak current at the AC output will be 62A which is beyond the 50A rating of the module.
We know that the 50A rating is a limit when Tvj is 175C, and the RMS current through mosfet should be between 30A and 35A. But we are not sure if 62A is within the FBSOA of the device.
The switching frequency is around 20kHz.
Can you please comment on the feasibility of such use of FF23MR12W1M1P_B11?
Also, it would be great if the FBSOA information can be provided. We can sign NDA if that is required.

Best,
Alex
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