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Switching frequency for device in PFC

November 24, 2020, 3:41 am
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Hello

I am developing a PFC and considering IKW40N65WR5 as a switching device.
My question is what’s the maximum switching frequency of IKW40N65WR5?
Is it okay to use for 60~70kHz?

Thanks in advance.
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IR2214 component calculations assistance

November 24, 2020, 7:43 am
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Hello all,

I am currently working with a PCB we have designed as a 3 phase inverter to do FOC control of a BLDC motor, aiming for 15kW (10KHz switching).

I am working through the calculations for the gate resistances but it isnt particularly clear where I obtain the total switching time for Rgon?? I have assumed that this is the sum of tr, tf, td(on) and td(off) from the IGBT datasheet?? (We are using 6x STGW40M120DF3 for the whole thing).

The design incorporates the optional gate resistor for the soft shutdown aswell as the series resistor at Vs and COM, I cant seem to find how these are calculated either? :)

The isolated power supply which is powering VDD on the three drivers is 2W, and Im also wondering if this is enough to run the three half-bridges sufficiently.

Any tips/pointers for this IC would be much appreciated.

Thanks all!

EDIT: I have grabbed the values from my spreadsheet to see if they check out:

For the above IGBTs (using 15V for VDD) I have calculated the following for the Rgon and Rgoff gate resistors, Rgon=4.863R (probably use 5R), Rgoff(max)=13.056R (Probably use 12R). I used a figure of 325ns for Tsw based on the above assumption.
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TOM SR registers update

November 24, 2020, 8:21 am
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I think this one lives in Pflash. I'm not currently using the PSPR/DSPR areas.
I can have a look into moving it there, see if that helps.

I'll also have a look at using the DMA more. I've noticed it takes quite a while to return my ADC results, I can probably speed that up using the DMA as well. I've seen there are code examples for this, I'll give it a go.

Thanks a lot for the suggestions!
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Data Access Overlay Function

November 24, 2020, 6:35 pm
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I want to use the Data Access Overlay(OVC) function with TC233.

Can you provide material or example source for this function?
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Sense2GOL, Debugger type is not switched to SEGGER

November 24, 2020, 6:44 pm
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hello,

To test the Sense2GOL in use of Infineon tool box, I have been following the instruction of Sense2GOL kit by downloading all the according files - Infineon tool box and JLINK USB Driver
However, at the step of selecting debugger type I cannot choose "SEGGER" which does not appears in the drop-down menu. only "DAP" is available.

What i have checked so far:
- USB connection for Sense2GOL is properly set
- Sense2GOL works fine.
- uC-Probe-XMC works well.

Could you please how to solve this issue?
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QAC License version is not working with free ADS with free tasking complier

November 24, 2020, 11:48 pm
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Hello Sir,
We are checking QAC in free tool Aurix development studio(ADS) with inbuilt tasking complier. QAC is generating an error. I have attached error we are facing in QAC. Our questions are as follow:
1) Do we required license version of Aurix development studio to perform QAC?
2) If we used free Aurix development than we are getting this error So do we need to purchase tasking complier license version to perform QAC in free Aurix Develop
Looking for your suggestion.

Thanks and regards,
Krunal Desai
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Using the ABM mode for TC397 chip

November 24, 2020, 11:56 pm
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Hi All,
How can I use ABM mode for TC397 chip? I found ABMHD description in docs, but I didn't find any ABMHD location description in the chip address space.
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aurix mtu example

November 25, 2020, 12:48 am
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Hello everyone,
I'm debugging mtu of tc212 in the reference of ads mtu example(MTU_MBIST_1_KIT_TC297_TFT). A const table in the example named IfxMtu_sramTable[] is used in ran test, which contains numBlocks, datasize and eccsize elements in it, but i didn't get any describes about these elements in UM, and got confused about it.
Anyone can tell me what mean of this element? And where to get the element of each function module?
Thanks!
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TC223 PFLASH Programming

November 25, 2020, 2:23 am
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Hi Alex,

I think the key here is we are getting a PROER (Protection error), not an SQER (Sequence Error), so I don't think that it is a read while doing a flash operation which is causing this particular error. Here is what could be causing a PROER:

* Write page executed on a sector with active write protection, of the flash module has active global read protection.
* Disable sector write protection when the passwords do not match

If the PFlash was busy due to the write, then we would expect a bus error and subsequently a CPU trap. What is FSR.RPROIN set to - 0 in your previous example, but FSR.PROIN is 1, so we have read or/and write protection configured. You also have bit 22 set - WPROIN1 is configured. One of these is likely to be the culprit. Can you run a disable write protection sequence, do your write, then resume protection?

Cheers,

Darren
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When does TLD5099EP (or TLD5098EP) detect a short to ground failure?

November 25, 2020, 4:13 am
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How are the conditions at the pins VFBL and VFBH?
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HOST and HSM accessing Their D Flashs Simultaneously on TC39x

November 25, 2020, 5:47 am
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Darren, MoD,

I checked my code, this region of memory is only accessed by CPU0 during the initialization, and after that there is no access happening. the problem appears when CPU0 try to read (or Blank check) the content of it's D flash.
the error is happening randomly because the same line of code is executed many time before the error appears. my driver always jump from one sector to another (when the current one full) and the error happen in different addresses randomly,
i erased the total flash via the debugger to make sure there is no dead cells or corrupted words, everything looks normal. and the error still appearing.

The HSM stops when the error due to an option in the debugger that allows me to halt the tricore when an error happens, and the call stack of the HSM is doing some normal function calls in my main function. i do not see any error on HSM.

maybe an important details is that when CPU0 stops the register D|[15] has the value 2 and i read that this is the Trap Identification Number (TIN) and A[11] has the address of the instruction that cause the trap and i can see also that it is correct.
So it looks like i'm dealing with Data Access Synchronous Error Trap, and i also have the CPU0_DSTR.LBE set to 1.

the question is how can i identify the cause of this trap ?
My D flashes are both in complement sensing mode and DF1 is HSM exclusive.
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ILLD Multican+ CAN Transmit problem

November 25, 2020, 8:38 pm
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Many problems can be solved by using this site that is a good source for collecting data. However, it will be useful to follow zety reviews that are now common among the users who have ideas related to it.
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AURIX TC27x, How to get out from Trap Handler?

November 26, 2020, 12:15 am
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You can manipulate the return address in register A11. You must get the instruction of address in register A11. Dependent of the size of this instruction (16 bit or 32 bit) you increase the register A11 by 2 or 4. When you now return from trap with rfe you will return to the next instruction after the faulty one.
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Aurix Development Studio bugged beyond repair

November 26, 2020, 12:56 am
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Good morning,

we released the version 1.2.4 of AURIX Development Studio, which fixes some of the issues you reported, in particular the random freeze of the debugger and the expression visualization.
The fix for the issue with the indexer and the stdio.h include will be released in the next version.

Thank you for your support.
Kind regards
Enrico
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MBIST issue

November 26, 2020, 4:26 am
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I want to understand how in the MBIST programming sequence it is mentioned that in order to check MBIST result I should check on all error bits in ECCD, shouldn't the MBIST already triggers the UCE during the MBIST itself? so it will be set already, how is checking this bit will let the MBIST pass if it is always set? what am I missing here?
can I check for ECCD.VAL bit to indicate if MBIST passed and not the Error bits? since VAL bit indicates whether there is a valid entry in error tracking registers?
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GTM DTM enable

November 26, 2020, 4:42 am
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hi,

i am working on the GTM, i tried the sample code and did the inverted signal generation by using signal level register , it is worked as expected, but i need to add the DTM in that signal, in iLLD i saw the DTM section is commented and expected to be
initiated by macros, is there anyplace where i can enable the DTM macro or i have to define? (this is the macro which driver asking to enable - IFXGTM_DTM_AVAILABLE.

where i can add the DeadTime count of each channel in iLLD which provide by infineon..

Thanks in advance
Mohamed Rahmathulla
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EASY Module 3-level development KIT

November 26, 2020, 8:38 am
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Hi Johanez,

Unfortunately for this module we do not have any development KIT or EVAL-board available.
Here you can find recommendations in regards to PCB design (dimensions of holes, tolerances and metallization) and press-in process.

BR
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ICE5QR0680AZ does not start!

November 26, 2020, 10:17 am
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Hello support,
I tried to replicate the "DEMO_5QR0680AZ_42W1" board with some minor modifications. Attached I send the schematic.
The difference is the feedback loop, where the 5V output is only controlled.
I did a production of 300 boards, and half of the boards, the chip ICE5QR0680AZ is in a state that tries to start, and after a while, sometimes it starts and sometimes it doesn't!
Am I doing something wrong? Do I have a feedback loop, calculated wrong?


Best regards
Ivo Bernardo
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DAVE: Debugging issue - Perhaps a Timeout

November 26, 2020, 10:19 am
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When debugging a program, I get something like a timeout.
On 2nd debug, it works.
Seems related to code size. Code size about 250k as per arm-none-eabi-size.
Erasing takes about 4 sec
Programming ? about the same. The progress bar gets about 1/2 way across then window disappears.
There is a brief message in the disassembly window.
Attachment 5314

If I issue a debug again, it all works. I think because the programming from before completed. So on 2nd debug, it compares ok and does its thing stopping at main.
Seems like Dave/Eclipse not waiting long enough for the programming.
Any ideas on what to do?
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Bas3005b02vh6327

November 26, 2020, 5:33 pm
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BAS3005B02VH6327 What does this model suffix H6327 mean? Is there a difference between H6327 and E6327?
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