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i2c help

November 4, 2016, 8:04 am
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Quote:
1. As I can see from the datasheet of INA3221 device, the slave address is 1000 00(A0)(R/W) (I hope it´s understandable). This A0 bit depends to which signal did you connect A0 pin. Can you verify that in your case this pin is connected to ground (this should set A0 bit to 0)?
Yes I do know that. The address I pass to the function is 0x80. I know that i2c only uses 7 bits for the address and that last bit is for R/W bit.
And I know the slave responds, because I get the ACK's.
Quote:
2. You could also include configuration of the output level for the both pins. It maybe be not necessary but you´re not doing anything wrong (as you can see the I2C protocol starts with both pins high). So just to the configuration structure add:
Code:
.output_level  = XMC_GPIO_OUTPUT_LEVEL_HIGH
done.

Quote:
3. You are requesting the read-out of the "Manufacturer ID" register as I can understand from your code. However, this register field is read-only so following code section is redundant:
Code:
XMC_I2C_CH_MasterTransmit(XMC_I2C0_CH1, 0xffU);
while((XMC_I2C_CH_GetStatusFlag(XMC_I2C0_CH1) & XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED) == 0U)
{
/* wait for ACK */
}
XMC_I2C_CH_ClearStatusFlag(XMC_I2C0_CH1, XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED);
Whoops.. it's actually the wrong address too.. .it's 0xFE that I want. So I just removed this.

Quote:
Also you can see that in the documentation where is stated:
Code:
To change the register pointer for a read operation, write a new value to the register pointer.
This write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register pointer byte.
No additional data are required.
Yup. Understood.

Quote:
4. This first "XMC_I2C_CH_MasterStop()" function call (right before "XMC_I2C_CH_MasterReceiveNack" function call) should not be there. You only transmit STOP bit at the end of transmission, as you done properly in your code at the end before "while" loop. So you should remove this function call.
Yeah that was stupid.
I just took out the while loop and now I just ask for two bytes which should give me 0x5449 according to the datasheet.
Quote:
Try to modify the code based on my suggestions and let me know do you still have issue.
Also, please let me know does your code successfully reaches "while" loop (meaning all the ACK bits are received and accepted). It would be nice if the issue is still present to screenshot the PSR_I2Cmode register just before and after you should receive data.
I have attached the latest code with your modifications. I've also attached a screenshot from my scope. You can see that the slave is answering me and I think I'm doing everything right.
That's why I'm perplexed.


Thanks for your help, I really appreciate it.
Attached Files
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Migrate option with ETHCAT_FWUPDATE_SSC_APPLICATION_XMC48

November 5, 2016, 3:44 am
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Hi,
This Application has only possibilities to migrate inside subfamily XMC4800,
but a have (want) to use subfamily XMC4300...
When can it be possible?
best regards
zbyno
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GUI_SEGGERLIBRARY app instance config - need help

November 5, 2016, 3:58 pm
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Hello,
I'm trying to interface custom tft display to xmc4500.
What should i write in the GUI_SEGGERLIBRARY -> Configure App instance->User Callback Functions
to don't finish with compilation errors?

Help file didn't helped me much in this case, examples are made for seps and there is no need to fill up these fields. (So It's sort of a bad example then :) )

Cheers!
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Cooling down a chip faster by using an invention from the automotive sector

November 6, 2016, 12:22 pm
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BMW started to drill holes in the breakes to cool them down faster.
Maybe it's possible to drill holes in the metalcorpus (Kühlrippen) that cools a processor.
What do you think?
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Hightec project for the TriBoard TC234

November 6, 2016, 11:47 pm
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Why don't you give both a try and decide for yourself?

Keep in mind that these are more or less restricted "free" editions and may not represent the full release in terms of features and performance.

Edit: I just saw that you're using a legacy TriCore and not an AURIX. We just support the AURIX with the free lite edition, our full release of course supports all available devices.
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XMC4500 SPI communictaion (as Master)

November 7, 2016, 8:02 am
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Using the iLLD for TC234 MultiCAN+

November 8, 2016, 4:03 am
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Hello,

I'm using the iLLD for TC234 MultiCAN+ and I've found that when you set up the baudrate (using the configuration structure provided by the iLLD), the final baudrate that is set up is x2.
I think that the driver is setting up wrong the BRP, TSEG1 and TSEG2 registers. Could it be?

Thanks in advance.

Alejandro.
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TLE5012B Angle Revolution Register

November 8, 2016, 4:15 am
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Hallo,

i have some question to the "Angle Revolution Register".

I am already reading the "Angle Value Register" very well and now i want to read the the revolution of my motor. The motor shaft runs with 50 rpm.

Here are my Code example:

void RevolutionOutput(void)
{
unsigned Frame_Counter;
int Num_Revolution;
int miso_data = (spi_read(angleRevolution_command));//& 0x7FFF);

Num_Revolution =0x00FF & miso_data;

Serial.print( "\t\t Aktueller Umlauf: ");
Serial.println(Num_Revolution);

}

My Problem is that the sensor give me every second turn around of my motor an increment.

Is it Important to use the Frame_Counter?

Please can anyone helb me?

Sorry for my bad english iam learing:)

best regards

Vita
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XMC1400 adc external multiplexer

November 8, 2016, 8:14 am
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I have a problem to set up the external multiplexer for channel 6 of the group 1 of the adc.

here my code of the multiplexer part:


WR_REG( VADC->EMUXSEL, VADC_EMUXSEL_EMUXGRP1_Msk, VADC_EMUXSEL_EMUXGRP1_Pos, 1 );

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXSET_Msk, VADC_G_EMUXCTR_EMUXSET_Pos, 6 ); // external multiplexer channel max - 1 is selected
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXCH_Msk, VADC_G_EMUXCTR_EMUXCH_Pos, CVADC_MULTIPLEXER_CHANNEL ); // external multiplexer is connected to adc channel 6
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXCOD_Msk, VADC_G_EMUXCTR_EMXCOD_Pos, 0 ); // emux coding is normal
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXMODE_Msk, VADC_G_EMUXCTR_EMUXMODE_Pos, 3 ); // emux mode is sequence mode
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXST_Msk, VADC_G_EMUXCTR_EMXST_Pos, 1); // sample time control for emux conversions
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXCSS_Msk, VADC_G_EMUXCTR_EMXCSS_Pos, 0 ); // emux channel select style, EMUXCH is channel number

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXWC_Msk, VADC_G_EMUXCTR_EMXWC_Pos, 1 ); // emux configuration write access enabled

VADC_G1->EMUXCTR = ulEmuxCtr;

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXWC_Msk, VADC_G_EMUXCTR_EMXWC_Pos, 0 ); // emux configuration write access disabled

Thx in advance for your help
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Help Setting up SPI Connection between XMC4700 and TLI4970 in DAVE

November 8, 2016, 11:12 am
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I am trying to set up a connection between an XMC4700 Relax Kit and a TLI4970 2Go current sensor. I have never set up a SPI connection before, so this is all pretty new to me. I added the SPI_Master app in DAVE, and in the configuration set it to half duplex, I assume any clock speed should work, so I set it to 200 kHz and the parity to odd. I believe I only need one way communication from the sensor to the board, as the sensor is triggered to send data based on the chip select, as far as I can tell. When I get to the advanced settings tab in the SPI_Master app, I start to get a bit lost. I changed the frame size to 16 as that is what size frames the sensor outputs, but besides that I am not quite sure what settings I will need. Is there a good example that goes through how to select these settings? Or is there somewhere that they are explained more in depth?

I also have a question about the pin allocations. When using the manual pin allocation tool in DAVE, it does not allow me to select both the designated SPI Clock and MISO pins that I was planning to use. Is there a reason for this? It seems pretty counter-intuitive to have ports specifically for clock and data and not allow me to map the pins to them. (I can map the clock to the correct pin, P3.9, but then it only allows me to map the MISO to P5.0 which is just a GPIO pin I believe).

Any help would be appreciated, I am very new to this.
Thank you.
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DMA problem using two timers

November 8, 2016, 12:33 pm
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Hi,

thank you for the tip with the shadow register transfer for all channels, but I think that´s not the problem. I found out that in my configuration the dma transfer for a timer register (CR2S) and the shadow register is only possible using channel 0 and 1
of dma0. I tested these two channels for the combinations (CCU80_CC80->CR2S and CCU80->GCSS) , (CCU80_CC81->CR2S and CCU80->GCSS) and (CCU80_CC82->CR2S and CCU80->GCSS) and it works. In every case I get one pwm via dma.
Why am I not able to get three pwms at the same time with the channel 0 (CCU80->GCSS), 1 (CCU80_CC80->CR2S), 2 (CCU80_CC81->CR2S), 3 (CCU80_CC82->CR2S). I changed the dma configuration of the channel 2 and 3 from M2P
to M2M transfering one array content to another to test whether the dma is working and it succeed. But in case of four M2P transfers on channel 2 and 3 only the last array value can be observed on the corresponding CR2S register.
It looks like these channels only do one dma action while the channel 0 and 1 are triggered continously.
I don´t know what the problem is, when I want to use dma transfer for all 3 pwms. Here is my simply code.

static XMC_DMA_CH_CONFIG_t DMA_CH_InitStructure0;
static XMC_DMA_CH_CONFIG_t DMA_CH_InitStructure1;
static XMC_DMA_CH_CONFIG_t DMA_CH_InitStructure2;
static XMC_DMA_CH_CONFIG_t DMA_CH_InitStructure3;

#define DMA_PERIOD_COUNT 1000
#define pwmShadowDmaChannel 0

#define pwmUhsDmaChannel 1
#define pwmVhsDmaChannel 2
#define pwmWhsDmaChannel 3

#define DMA_U_REG (&(CCU80_CC82->CR2S))
#define DMA_V_REG (&(CCU80_CC81->CR2S))
#define DMA_W_REG (&(CCU80_CC80->CR2S))
/************************************************** *************************************
* Declaration of variables (scope: module-local)
************************************************** *************************************/
static uint32_t dutyCycles_U_HS[DMA_PERIOD_COUNT];
static uint32_t dutyCycles_V_HS[DMA_PERIOD_COUNT];
static uint32_t dutyCycles_W_HS[DMA_PERIOD_COUNT];
static uint32_t shadow_transfer_enable;

void dma_InitPWM_U_HS(void);
void dma_InitPWM_V_HS(void);
void dma_InitPWM_W_HS(void);
void dma_InitPWM_TIMER(void);
void dma_InitShadowTransfer(void);
/************************************************** *************************************
* Implementation exported funcations (scope: global)
************************************************** *************************************/
void dma_Init(void){
uint32_t i;
for(i=0;i<DMA_PERIOD_COUNT;i++)
{
dutyCycles_U_HS[i]=i;
dutyCycles_W_HS[i]=i;
dutyCycles_V_HS[i]=i;
}
shadow_transfer_enable = XMC_CCU8_SHADOW_TRANSFER_SLICE_0 | XMC_CCU8_SHADOW_TRANSFER_SLICE_1 | XMC_CCU8_SHADOW_TRANSFER_SLICE_2;
//############
XMC_DMA_Init(XMC_DMA0);
//############
dma_InitShadowTransfer();
//############
dma_InitPWM_U_HS();
dma_InitPWM_V_HS();
dma_InitPWM_W_HS();
//############
XMC_DMA_CH_Enable(XMC_DMA0, pwmShadowDmaChannel);
XMC_DMA_CH_Enable(XMC_DMA0, pwmUhsDmaChannel);
XMC_DMA_CH_Enable(XMC_DMA0, pwmVhsDmaChannel);
XMC_DMA_CH_Enable(XMC_DMA0, pwmWhsDmaChannel);
//############
dma_InitPWM_TIMER();
}

void dma_InitShadowTransfer(void)
{
DMA_CH_InitStructure0.block_size = DMA_PERIOD_COUNT;
DMA_CH_InitStructure0.src_addr = (uint32_t)&shadow_transfer_enable;
DMA_CH_InitStructure0.dst_addr = (uint32_t)&CCU80->GCSS;
DMA_CH_InitStructure0.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure0.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure0.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
DMA_CH_InitStructure0.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
DMA_CH_InitStructure0.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure0.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure0.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA;
DMA_CH_InitStructure0.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD _DSTADR_RELOAD;
DMA_CH_InitStructure0.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE;
DMA_CH_InitStructure0.dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE;
DMA_CH_InitStructure0.dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0;
DMA_CH_InitStructure0.priority = XMC_DMA_CH_PRIORITY_0;
XMC_DMA_CH_Init(XMC_DMA0, pwmShadowDmaChannel, &DMA_CH_InitStructure0);
}

void dma_InitPWM_U_HS(void)
{
DMA_CH_InitStructure1.block_size = DMA_PERIOD_COUNT;
DMA_CH_InitStructure1.src_addr = (uint32_t)&dutyCycles_U_HS[0];
DMA_CH_InitStructure1.dst_addr = (uint32_t)DMA_U_REG;
DMA_CH_InitStructure1.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure1.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure1.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT;
DMA_CH_InitStructure1.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
DMA_CH_InitStructure1.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure1.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure1.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA;
DMA_CH_InitStructure1.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD _DSTADR_RELOAD;
DMA_CH_InitStructure1.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE;
DMA_CH_InitStructure1.dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE;
DMA_CH_InitStructure1.dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0;
DMA_CH_InitStructure1.priority = XMC_DMA_CH_PRIORITY_7;
XMC_DMA_CH_Init(XMC_DMA0, pwmUhsDmaChannel, &DMA_CH_InitStructure1);
}

void dma_InitPWM_V_HS(void)
{
DMA_CH_InitStructure2.block_size = DMA_PERIOD_COUNT;
DMA_CH_InitStructure2.src_addr = (uint32_t)&dutyCycles_V_HS[0];
DMA_CH_InitStructure2.dst_addr = (uint32_t)DMA_V_REG;
DMA_CH_InitStructure2.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure2.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure2.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT;
DMA_CH_InitStructure2.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
DMA_CH_InitStructure2.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure2.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure2.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA;
DMA_CH_InitStructure2.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD _DSTADR_RELOAD;
DMA_CH_InitStructure2.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE;
DMA_CH_InitStructure2.dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE;
DMA_CH_InitStructure2.dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0;
DMA_CH_InitStructure2.priority = XMC_DMA_CH_PRIORITY_7;
XMC_DMA_CH_Init(XMC_DMA0, pwmVhsDmaChannel, &DMA_CH_InitStructure2);
}

void dma_InitPWM_W_HS(void)
{
DMA_CH_InitStructure3.block_size = DMA_PERIOD_COUNT;
DMA_CH_InitStructure3.src_addr = (uint32_t)&dutyCycles_W_HS[0];
DMA_CH_InitStructure3.dst_addr = (uint32_t)DMA_W_REG;
DMA_CH_InitStructure3.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure3.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32;
DMA_CH_InitStructure3.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT;
DMA_CH_InitStructure3.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE;
DMA_CH_InitStructure3.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure3.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1;
DMA_CH_InitStructure3.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA;
DMA_CH_InitStructure3.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD _DSTADR_RELOAD;
DMA_CH_InitStructure3.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE;
DMA_CH_InitStructure3.dst_handshaking = XMC_DMA_CH_DST_HANDSHAKING_HARDWARE;
DMA_CH_InitStructure3.dst_peripheral_request = DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0;
DMA_CH_InitStructure3.priority =XMC_DMA_CH_PRIORITY_7;
XMC_DMA_CH_Init(XMC_DMA0, pwmWhsDmaChannel, &DMA_CH_InitStructure3);
}

void dma_InitPWM_TIMER(void)
{
XMC_CCU8_SLICE_EnableEvent(CCU80_CC80, XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH);
XMC_CCU8_SLICE_SetInterruptNode(CCU80_CC80, XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH, XMC_CCU8_SLICE_SR_ID_0);

XMC_CCU8_SLICE_SetTimerCompareMatch(CCU80_CC80, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, 0);
XMC_CCU8_SLICE_SetTimerCompareMatch(CCU80_CC81, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, 0);
XMC_CCU8_SLICE_SetTimerCompareMatch(CCU80_CC82, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, 0);
}

Can you give an advice? I`m despairing...
Kind regards
Sandro
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ETH_LWIP and SYSTIMER

November 8, 2016, 1:46 pm
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XMC4500 Socket server

November 8, 2016, 1:49 pm
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i have the same problem like ally, nobody knows that? Any examples?
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Eclipse J-Link and Relax Kit

November 8, 2016, 5:09 pm
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Hi,

I have a Relax kit (XMC4500) which I can successfully program/debug using DAVE. However, I would like to use my default Eclipse installation (the latest Eclipse release I have is Oxygen). I have set everything up and copied the working project from DAVE to my other Eclipse installation. The project compiles and the debugger connects to the target... but it hangs with the status "Launching HelloWorld Debug (99%)". I have checked the log file and it is almost identical to the one produced using DAVE, it just seems to stop when it gets to the point where it is about to program the device.

I have copied the linker script over as well and set the device using the Device (Packs feature installed). The memory map looks correct (I think).

Any help appreciated.
Attached Files
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UsbCanNode / USB CAN Monitor

November 9, 2016, 1:18 am
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Hi,
I want to announce that I started a project at https://github.com/dominikholler/UsbCanNode to monitor and stimulate the CAN bus using a XMC4700 by USB.
The software still has flaw, e.g. in hight traffic situations not all received frames are show to the user.
But maybe the code can help or inspire someone.
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Hall sensor and Encoder input to POSIF module of XMC1302

November 9, 2016, 2:06 am
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Hi,

As per the Application Note AP32289 the POSIF module can be set to only to any one mode from the following:

- 00B: Hall Sensor Mode
- 01B: Quadrature Decoder Mode
- 10B: Stand-alone Multi-Channel Mode
- 11B: Stand-alone Multi-Channel & Quadrature Decoder Mode

Does that mean only the hall sensor outputs or the encoder outputs be monitored by the POSIF module in the XMC1300 series but not both the outputs from both the sensors at the same time?
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DMA with Linked List

November 9, 2016, 6:45 am
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Dear all,

i have trouble to start a Linked List DMA Transfer triggered by an ADC event.
I´m using the XMC4500 hexagon board v2 with Dave 4 and the XMClib.

My Problem:
I´ve got a periodic synchronized ADC conversion (G0CH0, G0CH1 with G1CH0, G1CH1). The result event (of G0CH1) should trigger the DMA Transfer.
As there are two ADC Groups and therefore different group result registers, i would like to use a DMA Transfer with a linked list for the source/destination adress.

Here is my code:

Code:
uint16_t verify_ADC_Result1[2],verify_ADC_Result2[2];
XMC_DMA_LLI_t liste1, liste2;

void DmaInit(void)
{
        XMC_DMA_LLI_t liste1 =
        {
                .src_addr                                = (uint32_t)&VADC_G0->RES[0],
                .dst_addr                                = (uint32_t)&verify_ADC_Result1[0],
                .llp                                                = &liste2,
                .block_size                                = 8,
                .dst_transfer_width                    = XMC_DMA_CH_TRANSFER_WIDTH_16,
                .src_transfer_width            = XMC_DMA_CH_TRANSFER_WIDTH_16,
                .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                .dst_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                .src_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                .enable_dst_linked_list    = true,
                .enable_src_linked_list    = true,
                .transfer_flow                        = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
                .enable_src_gather                = true,
                .enable_dst_scatter                = false,
        };
        XMC_DMA_LLI_t liste2 =
        {
                .enable_interrupt                        = true,
                .src_addr                                = (uint32_t)&VADC_G1->RES[0],
                .dst_addr                                = (uint32_t)&verify_ADC_Result2[0],
                .llp                                                = 0,
                .block_size                                = 8,
                .dst_transfer_width                    = XMC_DMA_CH_TRANSFER_WIDTH_16,
                .src_transfer_width                    = XMC_DMA_CH_TRANSFER_WIDTH_16,
                .dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                .src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                .dst_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                .src_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                .enable_dst_linked_list    = true,
                .enable_src_linked_list    = true,
                .transfer_flow                        = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
                .enable_src_gather                = true,
                .enable_dst_scatter                = false,
        };

        XMC_DMA_CH_CONFIG_t GPDMA0_Ch0_config =
        {
                {
                  .enable_interrupt                = true,
                  .dst_transfer_width                = XMC_DMA_CH_TRANSFER_WIDTH_16,
                  .src_transfer_width                = XMC_DMA_CH_TRANSFER_WIDTH_16,
                  .dst_address_count_mode        = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                  .src_address_count_mode        = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
                  .dst_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                  .src_burst_length                = XMC_DMA_CH_BURST_LENGTH_8,
                  .enable_src_gather                = true,
                  .enable_dst_scatter                = false,
                  .transfer_flow                        = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
                },
          .src_gather_interval                = 1,
          .src_gather_count                = 1,
          .dst_scatter_interval                = 0,
          .dst_scatter_count                = 0,
          .block_size                                = 8,
          .transfer_type                        = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED,
          .priority                                        = XMC_DMA_CH_PRIORITY_7,
          .src_handshaking                = XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
          .src_peripheral_request        = DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1,
          .linked_list_pointer                = &liste1,
        };
        XMC_DMA_Init(XMC_DMA0);
        XMC_DMA_CH_Init(XMC_DMA0, 0, &GPDMA0_Ch0_config);
        XMC_DMA_CH_EnableEvent(XMC_DMA0, 0U, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
        NVIC_SetPriority(GPDMA0_0_IRQn, 9U);
        NVIC_EnableIRQ(GPDMA0_0_IRQn);
        XMC_DMA_CH_Enable(XMC_DMA0, 0);
}
Somehow i don´t get into my DMA interrupt handler and there is only one result in verify_ADC_Result1[0].
If i manually check verify_ADC_Result1[] and verify_ADC_Result2[] without the DMA by the ADC interrupt handler i get all results.
I just don´t get what is missing in my code.
The example did not help.
https://www.infineonforums.com/threa...-DAVE-4-XMCLib
Please help without Apps.

Kind regards Gera
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XMC4800: How to use both Ethercat + EBU

November 9, 2016, 7:00 am
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Hello,

we are evaluating XMC4800 for an ETHERCAT solution.
Beside ETHERCAT we need external bus Interface (EBU) for accessing FPGA.
16 Bit Adress/Data multiplexed

According to the Port I/O function table ( Datasheet 2.2.2.1)we have not found a valid solution for the pin assignment.

We have conflicts with PINs P0.4, P0.5 and P0.6
They are used for both EBU and ECAT and do not have any alternative mapping.

Any solution or is it impossible at all to use XMC4800 with ECAT and EBU ?

Many Thanks
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Emulated EEPROM

November 9, 2016, 8:03 am
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2 Questions:
1) Does Emulated EEPROM work on XMC4000 family?

2) I'm using E_EEPROM app on a XMC1302 device. Seems to work well.
When programming or updating a device, how can I preserve the contents of the EEPROM? I have cal data stored. It seems if I update the device using Dave and debug, the data is preserved. But if I use flasher app, XMCFlasher.jar, the EEPROM gets erased.
Any help is appreciated.
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DAVE example OPC UA Server

November 10, 2016, 1:46 am
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Hi,

everytime I try to connect to the example server (OPCUASERVER_LWIP_XMC47) I get a timeout exception. I only changed the IP, netmask and gateway adresses in main.h as described in the user manual.
The error occurs in function opcua_recv (opcua_server_tcpip.c) when calling UAServer_New_data_received.
It seems like the program runs into an infinite loop when calling this function for the third time. The first two times the function is called there are no errors and it returns OpcUa_Good.

I use the client which is included in the OPC Foundation´s .NET Stack and the XMC4700 Relax Kit.

Has anybody encountered a similiar problem?
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